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Wed, 26 Feb 2025 16:40:20 -0800 (PST) Received: from localhost ([1.146.90.134]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-aee7ddf2ac3sm164451a12.1.2025.02.26.16.40.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 26 Feb 2025 16:40:19 -0800 (PST) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Thu, 27 Feb 2025 10:40:11 +1000 Message-Id: Cc: "Daniel Henrique Barboza" , "Igor Mammedov" , "Richard Henderson" , "Helge Deller" , "Paolo Bonzini" , , "Zhao Liu" Subject: Re: [PATCH 1/4] target/ppc: drop ppc_tlb_invalidate_all from cpu_reset From: "Nicholas Piggin" To: =?utf-8?q?Alex_Benn=C3=A9e?= , X-Mailer: aerc 0.19.0 References: <20250225184628.3590671-1-alex.bennee@linaro.org> <20250225184628.3590671-2-alex.bennee@linaro.org> In-Reply-To: <20250225184628.3590671-2-alex.bennee@linaro.org> Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed Feb 26, 2025 at 4:46 AM AEST, Alex Benn=C3=A9e wrote: > The vCPU parent already triggers a tb_flush so this is un-needed: > > #0 tlb_flush_other_cpu (cpu=3D0x555556df8630) at ../../accel/tcg/cputl= b.c:419 > #1 0x0000555555ee38c9 in tcg_cpu_reset_hold (cpu=3D0x555556df8630) at = ../../accel/tcg/tcg-accel-ops.c:88 > #2 0x0000555555bc29e5 in cpu_exec_reset_hold (cpu=3D0x555556df8630) at= ../../system/cpus.c:208 > #3 0x00005555558932c3 in cpu_common_reset_hold (obj=3D0x555556df8630, = type=3DRESET_TYPE_COLD) at ../../hw/core/cpu-common.c:139 > #4 0x0000555555d480b1 in ppc_cpu_reset_hold (obj=3D0x555556df8630, typ= e=3DRESET_TYPE_COLD) at ../../target/ppc/cpu_init.c:7200 > #5 0x0000555555ef28f0 in resettable_phase_hold (obj=3D0x555556df8630, = opaque=3D0x0, type=3DRESET_TYPE_COLD) at ../../hw/core/resettable.c:162 > #6 0x0000555555ef24f4 in resettable_assert_reset (obj=3D0x555556df8630= , type=3DRESET_TYPE_COLD) at ../../hw/core/resettable.c:58 > #7 0x0000555555ef244c in resettable_reset (obj=3D0x555556df8630, type= =3DRESET_TYPE_COLD) at ../../hw/core/resettable.c:45 > #8 0x0000555555eef525 in device_cold_reset (dev=3D0x555556df8630) at .= ./../hw/core/qdev.c:239 > #9 0x00005555558931ab in cpu_reset (cpu=3D0x555556df8630) at ../../hw/= core/cpu-common.c:114 > #10 0x0000555555d1ec6b in ppce500_cpu_reset (opaque=3D0x555556df8630) a= t ../../hw/ppc/e500.c:785 > #11 0x000055555595c410 in legacy_reset_hold (obj=3D0x555556e6bbc0, type= =3DRESET_TYPE_COLD) at ../../hw/core/reset.c:76 > #12 0x0000555555ef28f0 in resettable_phase_hold (obj=3D0x555556e6bbc0, = opaque=3D0x0, type=3DRESET_TYPE_COLD) at ../../hw/core/resettable.c:162 > > Signed-off-by: Alex Benn=C3=A9e > --- > target/ppc/cpu_init.c | 3 --- > 1 file changed, 3 deletions(-) > > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c > index 062a6e85fb..f987b75c4f 100644 > --- a/target/ppc/cpu_init.c > +++ b/target/ppc/cpu_init.c > @@ -7242,9 +7242,6 @@ static void ppc_cpu_reset_hold(Object *obj, ResetTy= pe type) > if (tcg_enabled()) { > cpu_breakpoint_remove_all(cs, BP_CPU); > cpu_watchpoint_remove_all(cs, BP_CPU); > - if (env->mmu_model !=3D POWERPC_MMU_REAL) { > - ppc_tlb_invalidate_all(env); > - } This invalidates architectural TLBs (software-loaded TLBs) as well, so I=20 don't think we can get rid of it. Thanks, Nick