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Thu, 27 Feb 2025 01:05:55 -0800 (PST) Received: from localhost ([1.146.124.39]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-223501f9d63sm9559775ad.78.2025.02.27.01.05.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Feb 2025 01:05:54 -0800 (PST) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Thu, 27 Feb 2025 19:05:47 +1000 Message-Id: Cc: "Daniel Henrique Barboza" , "Igor Mammedov" , "Helge Deller" , "Paolo Bonzini" , , "Zhao Liu" Subject: Re: [PATCH 2/4] target/hppa: defer hppa_ptlbe until CPU starts running From: "Nicholas Piggin" To: "Richard Henderson" , =?utf-8?q?Alex_Benn=C3=A9e?= , X-Mailer: aerc 0.19.0 References: <20250225184628.3590671-1-alex.bennee@linaro.org> <20250225184628.3590671-3-alex.bennee@linaro.org> In-Reply-To: Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed Feb 26, 2025 at 5:38 AM AEST, Richard Henderson wrote: > On 2/25/25 11:33, Richard Henderson wrote: >> On 2/25/25 10:46, Alex Benn=C3=A9e wrote: >>> @@ -191,7 +199,7 @@ static void hppa_cpu_realizefn(DeviceState *dev, Er= ror **errp) >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 cpu->alarm_timer= =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 hppa_cpu_alarm_timer, cpu); >>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 hppa_ptlbe(&cpu->env); >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 async_run_on_cpu(cs, hppa_c= lear_ptlbe, RUN_ON_CPU_HOST_PTR(&cpu->env)); >>=20 >> Nack, this is emulation of hardware, not softmmu. > > Hmm. I see what you're thinking about though: this function, after reset= ting the data=20 > structures associated with the hardware emulation, also calls the softmmu= flush. > > If we absolutely need to do so, I suppose delaying the hardware emulation= flush to the=20 > work queue isn't the worst solution. This is where the hppa patch is mor= e correct than=20 > the ppc patch which completely eliminated the hardware emulation flush. Could we expose a function that performs the hardware state reset, and leave the TCG flushing to the TCG CPU reset? Thanks, Nick