Re: [RFC PATCH 1/3] accel/tcg: Option to permit incoherent translation block cache vs stores

["Nicholas Piggin" <npiggin@gmail.com>]

On Tue Apr 1, 2025 at 5:51 AM AEST, Richard Henderson wrote:
> On 3/31/25 10:54, Nicholas Piggin wrote:
>> Add an option TARGET_HAS_LAZY_ICACHE that does not invalidate TBs upon
>> store, but instead tracks that the icache has become incoherent, and
>> provides a tb_flush_incoherent() function that the target may call to
>> bring the TB back to coherency.
>
> We're not going to add another target specific ifdef, as we're working on removing all of 
> them.  If we were to add a feature like this, it would need to be done another way -- 
> probably via TCGCPUOps.

Sure.

> How much benefit did you measure for ppc for this?

It's noticable, I'll get some numbers. 

>> XXX: docs/devel/tcg.rst says that this is not permitted because TB must
>> be coherent with memory to handle exceptions correctly... I'm not sure
>> where this is, maybe it can be worked around and is not a showstopper?
>
> I presume that note was for x86.

It is actually for RISC it says. But it is very old so may not apply
any more.

Thanks,
Nick