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Wed, 16 Apr 2025 07:39:56 -0700 (PDT) Received: from localhost ([1.145.55.85]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c33fc4bd0sm14766275ad.184.2025.04.16.07.39.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 16 Apr 2025 07:39:55 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Thu, 17 Apr 2025 00:39:51 +1000 Message-Id: Subject: Re: [PATCH v4 082/163] tcg/ppc: Drop fallback constant loading in tcg_out_cmp From: "Nicholas Piggin" To: "Richard Henderson" , X-Mailer: aerc 0.19.0 References: <20250415192515.232910-1-richard.henderson@linaro.org> <20250415192515.232910-83-richard.henderson@linaro.org> In-Reply-To: <20250415192515.232910-83-richard.henderson@linaro.org> Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=npiggin@gmail.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed Apr 16, 2025 at 5:23 AM AEST, Richard Henderson wrote: > Use U and C constraints for brcond2 and setcond2, so that > tcg_out_cmp2 automatically passes in-range constants > to tcg_out_cmp. > > Signed-off-by: Richard Henderson > --- > tcg/ppc/tcg-target-con-set.h | 4 +-- > tcg/ppc/tcg-target.c.inc | 49 ++++++++++++------------------------ > 2 files changed, 18 insertions(+), 35 deletions(-) > > diff --git a/tcg/ppc/tcg-target-con-set.h b/tcg/ppc/tcg-target-con-set.h > index 77a1038d51..14cd217287 100644 > --- a/tcg/ppc/tcg-target-con-set.h > +++ b/tcg/ppc/tcg-target-con-set.h > @@ -15,7 +15,7 @@ C_O0_I2(r, rC) > C_O0_I2(v, r) > C_O0_I3(r, r, r) > C_O0_I3(o, m, r) > -C_O0_I4(r, r, ri, ri) > +C_O0_I4(r, r, rU, rC) > C_O0_I4(r, r, r, r) > C_O1_I1(r, r) > C_O1_I1(v, r) > @@ -34,7 +34,7 @@ C_O1_I2(v, v, v) > C_O1_I3(v, v, v, v) > C_O1_I4(v, v, v, vZM, v) > C_O1_I4(r, r, rC, rZ, rZ) > -C_O1_I4(r, r, r, ri, ri) > +C_O1_I4(r, r, r, rU, rC) > C_O2_I1(r, r, r) > C_N1O1_I1(o, m, r) > C_O2_I2(r, r, r, r) > diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc > index 339b3a0904..1782d05290 100644 > --- a/tcg/ppc/tcg-target.c.inc > +++ b/tcg/ppc/tcg-target.c.inc > @@ -1777,9 +1777,8 @@ static void tcg_out_test(TCGContext *s, TCGReg dest= , TCGReg arg1, TCGArg arg2, > } > =20 > static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg= 2, > - int const_arg2, int cr, TCGType type) > + bool const_arg2, int cr, TCGType type) > { > - int imm; > uint32_t op; > =20 > tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64 || type =3D=3D TCG_TY= PE_I32); > @@ -1796,18 +1795,15 @@ static void tcg_out_cmp(TCGContext *s, int cond, = TCGArg arg1, TCGArg arg2, > case TCG_COND_EQ: > case TCG_COND_NE: > if (const_arg2) { > - if ((int16_t) arg2 =3D=3D arg2) { > + if ((int16_t)arg2 =3D=3D arg2) { > op =3D CMPI; > - imm =3D 1; > - break; > - } else if ((uint16_t) arg2 =3D=3D arg2) { > - op =3D CMPLI; > - imm =3D 1; > break; > } > + tcg_debug_assert((uint16_t)arg2 =3D=3D arg2); > + op =3D CMPLI; > + break; > } > op =3D CMPL; > - imm =3D 0; > break; > =20 > case TCG_COND_TSTEQ: > @@ -1821,14 +1817,11 @@ static void tcg_out_cmp(TCGContext *s, int cond, = TCGArg arg1, TCGArg arg2, > case TCG_COND_LE: > case TCG_COND_GT: > if (const_arg2) { > - if ((int16_t) arg2 =3D=3D arg2) { > - op =3D CMPI; > - imm =3D 1; > - break; > - } > + tcg_debug_assert((int16_t)arg2 =3D=3D arg2); > + op =3D CMPI; > + break; > } > op =3D CMP; > - imm =3D 0; > break; > =20 > case TCG_COND_LTU: > @@ -1836,30 +1829,20 @@ static void tcg_out_cmp(TCGContext *s, int cond, = TCGArg arg1, TCGArg arg2, > case TCG_COND_LEU: > case TCG_COND_GTU: > if (const_arg2) { > - if ((uint16_t) arg2 =3D=3D arg2) { > - op =3D CMPLI; > - imm =3D 1; > - break; > - } > + tcg_debug_assert((uint16_t)arg2 =3D=3D arg2); > + op =3D CMPLI; > + break; > } > op =3D CMPL; > - imm =3D 0; > break; > =20 > default: > g_assert_not_reached(); > } > op |=3D BF(cr) | ((type =3D=3D TCG_TYPE_I64) << 21); > - > - if (imm) { > - tcg_out32(s, op | RA(arg1) | (arg2 & 0xffff)); > - } else { > - if (const_arg2) { > - tcg_out_movi(s, type, TCG_REG_R0, arg2); > - arg2 =3D TCG_REG_R0; > - } > - tcg_out32(s, op | RA(arg1) | RB(arg2)); > - } > + op |=3D RA(arg1); > + op |=3D const_arg2 ? arg2 & 0xffff : RB(arg2); Looks good as far as I can see (I don't know the backend very well). arg2 should not ever have upper bits set here (nor in the code you replaced), right? FWIW, Reviewed-by: Nicholas Piggin > + tcg_out32(s, op); > } > =20 > static void tcg_out_setcond_eq0(TCGContext *s, TCGType type, > @@ -4297,9 +4280,9 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsig= ned flags) > case INDEX_op_deposit_i64: > return C_O1_I2(r, 0, rZ); > case INDEX_op_brcond2_i32: > - return C_O0_I4(r, r, ri, ri); > + return C_O0_I4(r, r, rU, rC); > case INDEX_op_setcond2_i32: > - return C_O1_I4(r, r, r, ri, ri); > + return C_O1_I4(r, r, r, rU, rC); > case INDEX_op_add2_i64: > case INDEX_op_add2_i32: > return C_O2_I4(r, r, r, r, rI, rZM);