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Tue, 29 Apr 2025 17:00:53 -0700 (PDT) Received: from localhost ([1.145.95.178]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22db51023a4sm109082195ad.167.2025.04.29.17.00.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 29 Apr 2025 17:00:53 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Wed, 30 Apr 2025 10:00:48 +1000 Message-Id: Cc: , , "Daniel Henrique Barboza" , "Harsh Prateek Bora" Subject: Re: [PULL 1/2] target/ppc: Big-core scratch register fix From: "Nicholas Piggin" To: "Thomas Huth" , X-Mailer: aerc 0.19.0 References: <20250408124550.40485-1-npiggin@gmail.com> <20250408124550.40485-2-npiggin@gmail.com> <2d6dead5-f56c-43cf-b7d1-9567fef99616@redhat.com> In-Reply-To: <2d6dead5-f56c-43cf-b7d1-9567fef99616@redhat.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=npiggin@gmail.com; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu Apr 24, 2025 at 6:25 PM AEST, Thomas Huth wrote: > On 08/04/2025 14.45, Nicholas Piggin wrote: >> The per-core SCRATCH0-7 registers are shared between big cores, which >> was missed in the big-core implementation. It is difficult to model >> well with the big-core =3D=3D 2xPnvCore scheme we moved to, this fix >> uses the even PnvCore to store the scrach data. >>=20 >> Also remove a stray log message that came in with the same patch that >> introduced patch. >>=20 >> Fixes: c26504afd5f5c ("ppc/pnv: Add a big-core mode that joins two regul= ar cores") >> Cc: qemu-stable@nongnu.org >> Signed-off-by: Nicholas Piggin >> --- >> target/ppc/misc_helper.c | 9 ++++++++- >> 1 file changed, 8 insertions(+), 1 deletion(-) >>=20 >> diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c >> index 2d9512c116..46ae454afd 100644 >> --- a/target/ppc/misc_helper.c >> +++ b/target/ppc/misc_helper.c >> @@ -332,6 +332,10 @@ target_ulong helper_load_sprd(CPUPPCState *env) >> PnvCore *pc =3D pnv_cpu_state(cpu)->pnv_core; >> target_ulong sprc =3D env->spr[SPR_POWER_SPRC]; >> =20 >> + if (pc->big_core) { >> + pc =3D pnv_chip_find_core(pc->chip, CPU_CORE(pc)->core_id & ~0x= 1); >> + } >> + >> switch (sprc & 0x3e0) { >> case 0: /* SCRATCH0-3 */ >> case 1: /* SCRATCH4-7 */ >> @@ -368,6 +372,10 @@ void helper_store_sprd(CPUPPCState *env, target_ulo= ng val) >> PnvCore *pc =3D pnv_cpu_state(cpu)->pnv_core; >> int nr; >> =20 >> + if (pc->big_core) { >> + pc =3D pnv_chip_find_core(pc->chip, CPU_CORE(pc)->core_id & ~0x= 1); >> + } >> + > > Hi Nicholas, > > this patch breaks compilation when QEMU has been configured with=20 > "--without-default-devices" : > > FAILED: qemu-system-ppc64 > cc -m64 @qemu-system-ppc64.rsp > /usr/bin/ld: libqemu-ppc64-softmmu.a.p/target_ppc_misc_helper.c.o: in=20 > function `helper_load_sprd': > .../qemu/target/ppc/misc_helper.c:336:(.text+0xcab): undefined reference = to=20 > `pnv_chip_find_core' > /usr/bin/ld: libqemu-ppc64-softmmu.a.p/target_ppc_misc_helper.c.o: in=20 > function `helper_store_sprd': > .../qemu/target/ppc/misc_helper.c:376:(.text+0xda3): undefined reference = to=20 > `pnv_chip_find_core' > collect2: error: ld returned 1 exit status > > Could you please have a look? Thanks for the report, I have a hopefully simple fix just going through CI now... Do you know if there's any reason to exclude a bunch of targets in the build-without-defaults CI test? I wonder if we could just enable all, it shouldn't add too much time to build test. Thanks, Nick