[PULL 0/2] ppc-for-10.0-3 queue

[PULL 0/2] ppc-for-10.0-3 queue

[Nicholas Piggin]

The following changes since commit dfaecc04c46d298e9ee81bd0ca96d8754f1c27ed:

  Merge tag 'pull-riscv-to-apply-20250407-1' of https://github.com/alistair23/qemu into staging (2025-04-07 09:18:33 -0400)

are available in the Git repository at:

  https://gitlab.com/npiggin/qemu.git tags/pull-ppc-for-10.0-3-20250408

for you to fetch changes up to b3d47c8303b8be2c3693c5704012b3334741b7ed:

  target/ppc: Fix SPRC/SPRD SPRs for P9/10 (2025-04-08 20:52:49 +1000)

----------------------------------------------------------------
* Fix a couple of recent regressions in powernv SPRs

----------------------------------------------------------------
Nicholas Piggin (2):
      target/ppc: Big-core scratch register fix
      target/ppc: Fix SPRC/SPRD SPRs for P9/10

 target/ppc/cpu_init.c    | 23 ++++++++++++-----------
 target/ppc/misc_helper.c |  9 ++++++++-
 2 files changed, 20 insertions(+), 12 deletions(-)

[PULL 1/2] target/ppc: Big-core scratch register fix

[Nicholas Piggin]

The per-core SCRATCH0-7 registers are shared between big cores, which
was missed in the big-core implementation. It is difficult to model
well with the big-core == 2xPnvCore scheme we moved to, this fix
uses the even PnvCore to store the scrach data.

Also remove a stray log message that came in with the same patch that
introduced patch.

Fixes: c26504afd5f5c ("ppc/pnv: Add a big-core mode that joins two regular cores")
Cc: qemu-stable@nongnu.org
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 target/ppc/misc_helper.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
index 2d9512c116..46ae454afd 100644
--- a/target/ppc/misc_helper.c
+++ b/target/ppc/misc_helper.c
@@ -332,6 +332,10 @@ target_ulong helper_load_sprd(CPUPPCState *env)
     PnvCore *pc = pnv_cpu_state(cpu)->pnv_core;
     target_ulong sprc = env->spr[SPR_POWER_SPRC];
 
+    if (pc->big_core) {
+        pc = pnv_chip_find_core(pc->chip, CPU_CORE(pc)->core_id & ~0x1);
+    }
+
     switch (sprc & 0x3e0) {
     case 0: /* SCRATCH0-3 */
     case 1: /* SCRATCH4-7 */
@@ -368,6 +372,10 @@ void helper_store_sprd(CPUPPCState *env, target_ulong val)
     PnvCore *pc = pnv_cpu_state(cpu)->pnv_core;
     int nr;
 
+    if (pc->big_core) {
+        pc = pnv_chip_find_core(pc->chip, CPU_CORE(pc)->core_id & ~0x1);
+    }
+
     switch (sprc & 0x3e0) {
     case 0: /* SCRATCH0-3 */
     case 1: /* SCRATCH4-7 */
@@ -378,7 +386,6 @@ void helper_store_sprd(CPUPPCState *env, target_ulong val)
          * information. Could also dump these upon checkstop.
          */
         nr = (sprc >> 3) & 0x7;
-        qemu_log("SPRD write 0x" TARGET_FMT_lx " to SCRATCH%d\n", val, nr);
         pc->scratch[nr] = val;
         break;
     default:
-- 
2.47.1

Re: [PULL 1/2] target/ppc: Big-core scratch register fix

[Thomas Huth]

On 08/04/2025 14.45, Nicholas Piggin wrote:
> The per-core SCRATCH0-7 registers are shared between big cores, which
> was missed in the big-core implementation. It is difficult to model
> well with the big-core == 2xPnvCore scheme we moved to, this fix
> uses the even PnvCore to store the scrach data.
> 
> Also remove a stray log message that came in with the same patch that
> introduced patch.
> 
> Fixes: c26504afd5f5c ("ppc/pnv: Add a big-core mode that joins two regular cores")
> Cc: qemu-stable@nongnu.org
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
>   target/ppc/misc_helper.c | 9 ++++++++-
>   1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
> index 2d9512c116..46ae454afd 100644
> --- a/target/ppc/misc_helper.c
> +++ b/target/ppc/misc_helper.c
> @@ -332,6 +332,10 @@ target_ulong helper_load_sprd(CPUPPCState *env)
>       PnvCore *pc = pnv_cpu_state(cpu)->pnv_core;
>       target_ulong sprc = env->spr[SPR_POWER_SPRC];
>   
> +    if (pc->big_core) {
> +        pc = pnv_chip_find_core(pc->chip, CPU_CORE(pc)->core_id & ~0x1);
> +    }
> +
>       switch (sprc & 0x3e0) {
>       case 0: /* SCRATCH0-3 */
>       case 1: /* SCRATCH4-7 */
> @@ -368,6 +372,10 @@ void helper_store_sprd(CPUPPCState *env, target_ulong val)
>       PnvCore *pc = pnv_cpu_state(cpu)->pnv_core;
>       int nr;
>   
> +    if (pc->big_core) {
> +        pc = pnv_chip_find_core(pc->chip, CPU_CORE(pc)->core_id & ~0x1);
> +    }
> +

  Hi Nicholas,

this patch breaks compilation when QEMU has been configured with 
"--without-default-devices" :

FAILED: qemu-system-ppc64
cc -m64 @qemu-system-ppc64.rsp
/usr/bin/ld: libqemu-ppc64-softmmu.a.p/target_ppc_misc_helper.c.o: in 
function `helper_load_sprd':
.../qemu/target/ppc/misc_helper.c:336:(.text+0xcab): undefined reference to 
`pnv_chip_find_core'
/usr/bin/ld: libqemu-ppc64-softmmu.a.p/target_ppc_misc_helper.c.o: in 
function `helper_store_sprd':
.../qemu/target/ppc/misc_helper.c:376:(.text+0xda3): undefined reference to 
`pnv_chip_find_core'
collect2: error: ld returned 1 exit status

Could you please have a look?

  Thanks,
   Thomas

Re: [PULL 1/2] target/ppc: Big-core scratch register fix

[Nicholas Piggin]

On Thu Apr 24, 2025 at 6:25 PM AEST, Thomas Huth wrote:
> On 08/04/2025 14.45, Nicholas Piggin wrote:
>> The per-core SCRATCH0-7 registers are shared between big cores, which
>> was missed in the big-core implementation. It is difficult to model
>> well with the big-core == 2xPnvCore scheme we moved to, this fix
>> uses the even PnvCore to store the scrach data.
>> 
>> Also remove a stray log message that came in with the same patch that
>> introduced patch.
>> 
>> Fixes: c26504afd5f5c ("ppc/pnv: Add a big-core mode that joins two regular cores")
>> Cc: qemu-stable@nongnu.org
>> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
>> ---
>>   target/ppc/misc_helper.c | 9 ++++++++-
>>   1 file changed, 8 insertions(+), 1 deletion(-)
>> 
>> diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
>> index 2d9512c116..46ae454afd 100644
>> --- a/target/ppc/misc_helper.c
>> +++ b/target/ppc/misc_helper.c
>> @@ -332,6 +332,10 @@ target_ulong helper_load_sprd(CPUPPCState *env)
>>       PnvCore *pc = pnv_cpu_state(cpu)->pnv_core;
>>       target_ulong sprc = env->spr[SPR_POWER_SPRC];
>>   
>> +    if (pc->big_core) {
>> +        pc = pnv_chip_find_core(pc->chip, CPU_CORE(pc)->core_id & ~0x1);
>> +    }
>> +
>>       switch (sprc & 0x3e0) {
>>       case 0: /* SCRATCH0-3 */
>>       case 1: /* SCRATCH4-7 */
>> @@ -368,6 +372,10 @@ void helper_store_sprd(CPUPPCState *env, target_ulong val)
>>       PnvCore *pc = pnv_cpu_state(cpu)->pnv_core;
>>       int nr;
>>   
>> +    if (pc->big_core) {
>> +        pc = pnv_chip_find_core(pc->chip, CPU_CORE(pc)->core_id & ~0x1);
>> +    }
>> +
>
>   Hi Nicholas,
>
> this patch breaks compilation when QEMU has been configured with 
> "--without-default-devices" :
>
> FAILED: qemu-system-ppc64
> cc -m64 @qemu-system-ppc64.rsp
> /usr/bin/ld: libqemu-ppc64-softmmu.a.p/target_ppc_misc_helper.c.o: in 
> function `helper_load_sprd':
> .../qemu/target/ppc/misc_helper.c:336:(.text+0xcab): undefined reference to 
> `pnv_chip_find_core'
> /usr/bin/ld: libqemu-ppc64-softmmu.a.p/target_ppc_misc_helper.c.o: in 
> function `helper_store_sprd':
> .../qemu/target/ppc/misc_helper.c:376:(.text+0xda3): undefined reference to 
> `pnv_chip_find_core'
> collect2: error: ld returned 1 exit status
>
> Could you please have a look?

Thanks for the report, I have a hopefully simple fix just going through
CI now... Do you know if there's any reason to exclude a bunch of
targets in the build-without-defaults CI test? I wonder if we could just
enable all, it shouldn't add too much time to build test.

Thanks,
Nick

Re: [PULL 1/2] target/ppc: Big-core scratch register fix

[Thomas Huth]

On 30/04/2025 02.00, Nicholas Piggin wrote:
> On Thu Apr 24, 2025 at 6:25 PM AEST, Thomas Huth wrote:
>> On 08/04/2025 14.45, Nicholas Piggin wrote:
>>> The per-core SCRATCH0-7 registers are shared between big cores, which
>>> was missed in the big-core implementation. It is difficult to model
>>> well with the big-core == 2xPnvCore scheme we moved to, this fix
>>> uses the even PnvCore to store the scrach data.
>>>
>>> Also remove a stray log message that came in with the same patch that
>>> introduced patch.
>>>
>>> Fixes: c26504afd5f5c ("ppc/pnv: Add a big-core mode that joins two regular cores")
>>> Cc: qemu-stable@nongnu.org
>>> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
>>> ---
>>>    target/ppc/misc_helper.c | 9 ++++++++-
>>>    1 file changed, 8 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
>>> index 2d9512c116..46ae454afd 100644
>>> --- a/target/ppc/misc_helper.c
>>> +++ b/target/ppc/misc_helper.c
>>> @@ -332,6 +332,10 @@ target_ulong helper_load_sprd(CPUPPCState *env)
>>>        PnvCore *pc = pnv_cpu_state(cpu)->pnv_core;
>>>        target_ulong sprc = env->spr[SPR_POWER_SPRC];
>>>    
>>> +    if (pc->big_core) {
>>> +        pc = pnv_chip_find_core(pc->chip, CPU_CORE(pc)->core_id & ~0x1);
>>> +    }
>>> +
>>>        switch (sprc & 0x3e0) {
>>>        case 0: /* SCRATCH0-3 */
>>>        case 1: /* SCRATCH4-7 */
>>> @@ -368,6 +372,10 @@ void helper_store_sprd(CPUPPCState *env, target_ulong val)
>>>        PnvCore *pc = pnv_cpu_state(cpu)->pnv_core;
>>>        int nr;
>>>    
>>> +    if (pc->big_core) {
>>> +        pc = pnv_chip_find_core(pc->chip, CPU_CORE(pc)->core_id & ~0x1);
>>> +    }
>>> +
>>
>>    Hi Nicholas,
>>
>> this patch breaks compilation when QEMU has been configured with
>> "--without-default-devices" :
>>
>> FAILED: qemu-system-ppc64
>> cc -m64 @qemu-system-ppc64.rsp
>> /usr/bin/ld: libqemu-ppc64-softmmu.a.p/target_ppc_misc_helper.c.o: in
>> function `helper_load_sprd':
>> .../qemu/target/ppc/misc_helper.c:336:(.text+0xcab): undefined reference to
>> `pnv_chip_find_core'
>> /usr/bin/ld: libqemu-ppc64-softmmu.a.p/target_ppc_misc_helper.c.o: in
>> function `helper_store_sprd':
>> .../qemu/target/ppc/misc_helper.c:376:(.text+0xda3): undefined reference to
>> `pnv_chip_find_core'
>> collect2: error: ld returned 1 exit status
>>
>> Could you please have a look?
> 
> Thanks for the report, I have a hopefully simple fix just going through
> CI now... Do you know if there's any reason to exclude a bunch of
> targets in the build-without-defaults CI test? I wonder if we could just
> enable all, it shouldn't add too much time to build test.

I think that setting has been added back then when we still built all 
machines with --without-default-devices and only disabled the optional 
devices. Then Paolo once cleaned this up (see commit bf616ce47be6802bbe7d 
for example), so that all boards now get disabled by default, too. Since 
that point in time, the runtime of the job is likely much decreased. So yes, 
I think we could nowadays add more targets to that job without risking to 
hit the timeout again. Could you maybe suggest a patch?

  Thanks,
   Thomas

[PULL 2/2] target/ppc: Fix SPRC/SPRD SPRs for P9/10

[Nicholas Piggin]

Commit 60d30cff847 ("target/ppc: Move SPR indirect registers into
PnvCore") was mismerged and moved the SPRs to power8-only, instead
of power9/10-only.

Fixes: 60d30cff847 ("target/ppc: Move SPR indirect registers into PnvCore")
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Cc: qemu-stable@nongnu.org
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 target/ppc/cpu_init.c | 23 ++++++++++++-----------
 1 file changed, 12 insertions(+), 11 deletions(-)

diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 7decc09aec..f81cb680fc 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -5801,6 +5801,18 @@ static void register_power9_book4_sprs(CPUPPCState *env)
                  &spr_read_generic, &spr_write_generic,
                  &spr_read_generic, &spr_write_generic,
                  0x00000000);
+
+    /* SPRC/SPRD exist in earlier CPUs but only tested on POWER9/10 */
+    spr_register_hv(env, SPR_POWER_SPRC, "SPRC",
+                 SPR_NOACCESS, SPR_NOACCESS,
+                 SPR_NOACCESS, SPR_NOACCESS,
+                 &spr_read_generic, &spr_write_sprc,
+                 0x00000000);
+    spr_register_hv(env, SPR_POWER_SPRD, "SPRD",
+                 SPR_NOACCESS, SPR_NOACCESS,
+                 SPR_NOACCESS, SPR_NOACCESS,
+                 &spr_read_sprd, &spr_write_sprd,
+                 0x00000000);
 #endif
 }
 
@@ -5822,17 +5834,6 @@ static void register_power8_book4_sprs(CPUPPCState *env)
                      SPR_NOACCESS, SPR_NOACCESS,
                      &spr_read_generic, &spr_write_generic,
                      KVM_REG_PPC_WORT, 0);
-    /* SPRC/SPRD exist in earlier CPUs but only tested on POWER9/10 */
-    spr_register_hv(env, SPR_POWER_SPRC, "SPRC",
-                 SPR_NOACCESS, SPR_NOACCESS,
-                 SPR_NOACCESS, SPR_NOACCESS,
-                 &spr_read_generic, &spr_write_sprc,
-                 0x00000000);
-    spr_register_hv(env, SPR_POWER_SPRD, "SPRD",
-                 SPR_NOACCESS, SPR_NOACCESS,
-                 SPR_NOACCESS, SPR_NOACCESS,
-                 &spr_read_sprd, &spr_write_sprd,
-                 0x00000000);
 #endif
 }
 
-- 
2.47.1

Re: [PULL 0/2] ppc-for-10.0-3 queue

[Stefan Hajnoczi]

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Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any user-visible changes.

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