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Thu, 15 May 2025 16:46:59 -0700 (PDT) Received: from localhost ([118.209.229.237]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-231d4ed540dsm3176265ad.218.2025.05.15.16.46.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 15 May 2025 16:46:59 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Fri, 16 May 2025 09:46:54 +1000 Message-Id: From: "Nicholas Piggin" To: "Mike Kowal" , Cc: , =?utf-8?q?Fr=C3=A9d=C3=A9ric_Barrat?= , "Glenn Miles" , "Caleb Schlossin" Subject: Re: [PATCH 32/50] ppc/xive: Split xive recompute from IPB function X-Mailer: aerc 0.19.0 References: <20250512031100.439842-1-npiggin@gmail.com> <20250512031100.439842-33-npiggin@gmail.com> <015a40ec-5685-4572-a981-29fc40fefcda@linux.ibm.com> In-Reply-To: <015a40ec-5685-4572-a981-29fc40fefcda@linux.ibm.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu May 15, 2025 at 6:42 AM AEST, Mike Kowal wrote: > > On 5/11/2025 10:10 PM, Nicholas Piggin wrote: >> Further split xive_tctx_pipr_update() by splitting out a new function >> that is used to re-compute the PIPR from IPB. This is generally only >> used with XIVE1, because group interrputs require more logic. > > > Previous upstreaming was focused only on XIVE2 as not to impact users of= =20 > XIVE1. Yeah it's a balancing act. I didn't want xive1 to diverge too much in basic APIs like the PIPR updating. So long as powernv9 gets some basic OPAL testing, hopefully it should be okay. > > But I assume this does not hurt anything. > > Reviewed-by: Michael Kowal Thanks, Nick > > Thanks,=C2=A0 MAK > > >> >> Signed-off-by: Nicholas Piggin >> --- >> hw/intc/xive.c | 25 ++++++++++++++++++++++--- >> 1 file changed, 22 insertions(+), 3 deletions(-) >> >> diff --git a/hw/intc/xive.c b/hw/intc/xive.c >> index 25f6c69c44..5ff1b8f024 100644 >> --- a/hw/intc/xive.c >> +++ b/hw/intc/xive.c >> @@ -225,6 +225,20 @@ void xive_tctx_pipr_update(XiveTCTX *tctx, uint8_t = ring, uint8_t priority, >> xive_tctx_notify(tctx, ring, group_level); >> } >> =20 >> +static void xive_tctx_pipr_recompute_from_ipb(XiveTCTX *tctx, uint8_t r= ing) >> +{ >> + /* HV_POOL ring uses HV_PHYS NSR, CPPR and PIPR registers */ >> + uint8_t alt_ring =3D (ring =3D=3D TM_QW2_HV_POOL) ? TM_QW3_HV_PHYS = : ring; >> + uint8_t *aregs =3D &tctx->regs[alt_ring]; >> + uint8_t *regs =3D &tctx->regs[ring]; >> + >> + /* Does not support a presented group interrupt */ >> + g_assert(!xive_nsr_indicates_group_exception(alt_ring, aregs[TM_NSR= ])); >> + >> + aregs[TM_PIPR] =3D xive_ipb_to_pipr(regs[TM_IPB]); >> + xive_tctx_notify(tctx, ring, 0); >> +} >> + >> void xive_tctx_pipr_present(XiveTCTX *tctx, uint8_t ring, uint8_t prio= rity, >> uint8_t group_level) >> { >> @@ -517,7 +531,12 @@ static void xive_tm_set_os_lgs(XivePresenter *xptr,= XiveTCTX *tctx, >> static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx= , >> hwaddr offset, uint64_t value, unsi= gned size) >> { >> - xive_tctx_pipr_update(tctx, TM_QW1_OS, value & 0xff, 0); >> + uint8_t ring =3D TM_QW1_OS; >> + uint8_t *regs =3D &tctx->regs[ring]; >> + >> + /* XXX: how should this work exactly? */ >> + regs[TM_IPB] |=3D xive_priority_to_ipb(value & 0xff); >> + xive_tctx_pipr_recompute_from_ipb(tctx, ring); >> } >> =20 >> static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk, >> @@ -601,14 +620,14 @@ static void xive_tctx_need_resend(XiveRouter *xrtr= , XiveTCTX *tctx, >> } >> =20 >> /* >> - * Always call xive_tctx_pipr_update(). Even if there were no >> + * Always call xive_tctx_recompute_from_ipb(). Even if there were n= o >> * escalation triggered, there could be a pending interrupt which >> * was saved when the context was pulled and that we need to take >> * into account by recalculating the PIPR (which is not >> * saved/restored). >> * It will also raise the External interrupt signal if needed. >> */ >> - xive_tctx_pipr_update(tctx, TM_QW1_OS, 0xFF, 0); /* fxb */ >> + xive_tctx_pipr_recompute_from_ipb(tctx, TM_QW1_OS); /* fxb */ >> } >> =20 >> /*