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Thu, 15 May 2025 17:05:57 -0700 (PDT) Received: from localhost ([118.209.229.237]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-231d4e97dadsm3403775ad.141.2025.05.15.17.05.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 15 May 2025 17:05:56 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Fri, 16 May 2025 10:05:51 +1000 Message-Id: Cc: , =?utf-8?q?Fr=C3=A9d=C3=A9ric_Barrat?= , "Glenn Miles" , "Michael Kowal" , "Caleb Schlossin" , "Glenn Miles" Subject: Re: [PATCH 17/50] pnv/xive2: Support ESB Escalation From: "Nicholas Piggin" To: "Nicholas Piggin" , X-Mailer: aerc 0.19.0 References: <20250512031100.439842-1-npiggin@gmail.com> <20250512031100.439842-18-npiggin@gmail.com> In-Reply-To: <20250512031100.439842-18-npiggin@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=npiggin@gmail.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon May 12, 2025 at 1:10 PM AEST, Nicholas Piggin wrote: > From: Glenn Miles > > Add support for XIVE ESB Interrupt Escalation. > > Suggested-by: Michael Kowal > [This change was taken from a patch provided by Michael Kowal.] > Signed-off-by: Glenn Miles > --- > hw/intc/xive2.c | 62 ++++++++++++++++++++++++++++++------- > include/hw/ppc/xive2.h | 1 + > include/hw/ppc/xive2_regs.h | 13 +++++--- > 3 files changed, 59 insertions(+), 17 deletions(-) > > diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c > index de139dcfbf..0993e792cc 100644 > --- a/hw/intc/xive2.c > +++ b/hw/intc/xive2.c > @@ -1552,18 +1552,39 @@ do_escalation: > } > } > =20 > - /* > - * The END trigger becomes an Escalation trigger > - */ > - xive2_router_end_notify(xrtr, > - xive_get_field32(END2_W4_END_BLOCK, end.w= 4), > - xive_get_field32(END2_W4_ESC_END_INDEX, end.w= 4), > - xive_get_field32(END2_W5_ESC_END_DATA, end.w= 5)); > + if (xive2_end_is_escalate_end(&end)) { > + /* > + * Perform END Adaptive escalation processing > + * The END trigger becomes an Escalation trigger > + */ > + xive2_router_end_notify(xrtr, > + xive_get_field32(END2_W4_END_BLOCK, e= nd.w4), > + xive_get_field32(END2_W4_ESC_END_INDEX, e= nd.w4), > + xive_get_field32(END2_W5_ESC_END_DATA, e= nd.w5)); > + } /* end END adaptive escalation */ > + > + else { > + uint32_t lisn; /* Logical Interrupt Source Number *= / > + > + /* > + * Perform ESB escalation processing > + * E[N] =3D=3D 1 --> N > + * Req[Block] <- E[ESB_Block] > + * Req[Index] <- E[ESB_Index] > + * Req[Offset] <- 0x000 > + * Execute Req command > + */ > + lisn =3D XIVE_EAS(xive_get_field32(END2_W4_END_BLOCK, end.w4= ), > + xive_get_field32(END2_W4_ESC_END_INDEX, end.w4))= ; > + > + xive2_notify(xrtr, lisn, true /* pq_checked */); Sorry I forgot to squash in a fix for the issues here. These should be _ESB_ constants not _END_, and we believe pq_checked should be false here so the ESB state machine is run. https://lore.kernel.org/qemu-devel/D8CFK7Z5AJF8.ALT8MMH6EYYT@gmail.com/ I think we took discussion offline after that but that was the conclusion. I will sqash that fix in here. With that, Reviewed-by: Nicholas Piggin I also wonder if Mike should be author of this patch since that's what the note indicates? Or co-author? Better give your Signed-off-by too, if so. Thanks, Nick