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Thu, 15 May 2025 17:06:43 -0700 (PDT) Received: from localhost ([118.209.229.237]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-742a9878b53sm366798b3a.152.2025.05.15.17.06.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 15 May 2025 17:06:42 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Fri, 16 May 2025 10:06:37 +1000 Message-Id: Cc: , =?utf-8?q?Fr=C3=A9d=C3=A9ric_Barrat?= , "Glenn Miles" , "Michael Kowal" , "Caleb Schlossin" Subject: Re: [PATCH 03/50] ppc/xive2: Fix calculation of END queue sizes From: "Nicholas Piggin" To: "Nicholas Piggin" , X-Mailer: aerc 0.19.0 References: <20250512031100.439842-1-npiggin@gmail.com> <20250512031100.439842-4-npiggin@gmail.com> In-Reply-To: <20250512031100.439842-4-npiggin@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=npiggin@gmail.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon May 12, 2025 at 1:10 PM AEST, Nicholas Piggin wrote: > From: Glenn Miles > > The queue size of an Event Notification Descriptor (END) > is determined by the 'cl' and QsZ fields of the END. > If the cl field is 1, then the queue size (in bytes) will > be the size of a cache line 128B * 2^QsZ and QsZ is limited > to 4. Otherwise, it will be 4096B * 2^QsZ with QsZ limited > to 12. > Reviewed-by: Nicholas Piggin > Fixes: f8a233dedf2 ("ppc/xive2: Introduce a XIVE2 core framework") > Signed-off-by: Glenn Miles > --- > hw/intc/xive2.c | 25 +++++++++++++++++++------ > include/hw/ppc/xive2_regs.h | 1 + > 2 files changed, 20 insertions(+), 6 deletions(-) > > diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c > index 7d584dfafa..790152a2a6 100644 > --- a/hw/intc/xive2.c > +++ b/hw/intc/xive2.c > @@ -188,12 +188,27 @@ void xive2_eas_pic_print_info(Xive2Eas *eas, uint32= _t lisn, GString *buf) > (uint32_t) xive_get_field64(EAS2_END_DATA, ea= s->w)); > } > =20 > +#define XIVE2_QSIZE_CHUNK_CL 128 > +#define XIVE2_QSIZE_CHUNK_4k 4096 > +/* Calculate max number of queue entries for an END */ > +static uint32_t xive2_end_get_qentries(Xive2End *end) > +{ > + uint32_t w3 =3D end->w3; > + uint32_t qsize =3D xive_get_field32(END2_W3_QSIZE, w3); > + if (xive_get_field32(END2_W3_CL, w3)) { > + g_assert(qsize <=3D 4); > + return (XIVE2_QSIZE_CHUNK_CL << qsize) / sizeof(uint32_t); > + } else { > + g_assert(qsize <=3D 12); > + return (XIVE2_QSIZE_CHUNK_4k << qsize) / sizeof(uint32_t); > + } > +} > + > void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width, GStri= ng *buf) > { > uint64_t qaddr_base =3D xive2_end_qaddr(end); > - uint32_t qsize =3D xive_get_field32(END2_W3_QSIZE, end->w3); > uint32_t qindex =3D xive_get_field32(END2_W1_PAGE_OFF, end->w1); > - uint32_t qentries =3D 1 << (qsize + 10); > + uint32_t qentries =3D xive2_end_get_qentries(end); > int i; > =20 > /* > @@ -223,8 +238,7 @@ void xive2_end_pic_print_info(Xive2End *end, uint32_t= end_idx, GString *buf) > uint64_t qaddr_base =3D xive2_end_qaddr(end); > uint32_t qindex =3D xive_get_field32(END2_W1_PAGE_OFF, end->w1); > uint32_t qgen =3D xive_get_field32(END2_W1_GENERATION, end->w1); > - uint32_t qsize =3D xive_get_field32(END2_W3_QSIZE, end->w3); > - uint32_t qentries =3D 1 << (qsize + 10); > + uint32_t qentries =3D xive2_end_get_qentries(end); > =20 > uint32_t nvx_blk =3D xive_get_field32(END2_W6_VP_BLOCK, end->w6); > uint32_t nvx_idx =3D xive_get_field32(END2_W6_VP_OFFSET, end->w6); > @@ -341,13 +355,12 @@ void xive2_nvgc_pic_print_info(Xive2Nvgc *nvgc, uin= t32_t nvgc_idx, GString *buf) > static void xive2_end_enqueue(Xive2End *end, uint32_t data) > { > uint64_t qaddr_base =3D xive2_end_qaddr(end); > - uint32_t qsize =3D xive_get_field32(END2_W3_QSIZE, end->w3); > uint32_t qindex =3D xive_get_field32(END2_W1_PAGE_OFF, end->w1); > uint32_t qgen =3D xive_get_field32(END2_W1_GENERATION, end->w1); > =20 > uint64_t qaddr =3D qaddr_base + (qindex << 2); > uint32_t qdata =3D cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); > - uint32_t qentries =3D 1 << (qsize + 10); > + uint32_t qentries =3D xive2_end_get_qentries(end); > =20 > if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qd= ata), > MEMTXATTRS_UNSPECIFIED)) { > diff --git a/include/hw/ppc/xive2_regs.h b/include/hw/ppc/xive2_regs.h > index b11395c563..3c28de8a30 100644 > --- a/include/hw/ppc/xive2_regs.h > +++ b/include/hw/ppc/xive2_regs.h > @@ -87,6 +87,7 @@ typedef struct Xive2End { > #define END2_W2_EQ_ADDR_HI PPC_BITMASK32(8, 31) > uint32_t w3; > #define END2_W3_EQ_ADDR_LO PPC_BITMASK32(0, 24) > +#define END2_W3_CL PPC_BIT32(27) > #define END2_W3_QSIZE PPC_BITMASK32(28, 31) > uint32_t w4; > #define END2_W4_END_BLOCK PPC_BITMASK32(4, 7)