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Thu, 15 May 2025 17:12:51 -0700 (PDT) Received: from localhost ([118.209.229.237]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-231d4e97db8sm3458455ad.110.2025.05.15.17.12.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 15 May 2025 17:12:51 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Fri, 16 May 2025 10:12:45 +1000 Message-Id: Subject: Re: [PATCH 08/50] ppc/xive2: Use fair irq target search algorithm From: "Nicholas Piggin" To: "Nicholas Piggin" , Cc: , =?utf-8?q?Fr=C3=A9d=C3=A9ric_Barrat?= , "Glenn Miles" , "Michael Kowal" , "Caleb Schlossin" X-Mailer: aerc 0.19.0 References: <20250512031100.439842-1-npiggin@gmail.com> <20250512031100.439842-9-npiggin@gmail.com> In-Reply-To: <20250512031100.439842-9-npiggin@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon May 12, 2025 at 1:10 PM AEST, Nicholas Piggin wrote: > From: Glenn Miles > > The current xive algorithm for finding a matching group vCPU > target always uses the first vCPU found. And, since it always > starts the search with thread 0 of a core, thread 0 is almost > always used to handle group interrupts. This can lead to additional > interrupt latency and poor performance for interrupt intensive > work loads. > > Changing this to use a simple round-robin algorithm for deciding which > thread number to use when starting a search, which leads to a more > distributed use of threads for handling group interrupts. > Does hardware always do the "histogram" distribution? I wonder if there would be any performance benefit to do something like send to an idle thread/core with preference. I guess the xive controller might have a difficult time querying the state of a bunch of cores before sending so it's probably not practical for real hardware. In any case this is a nice improvement for group delivery. Reviewed-by: Nicholas Piggin > [npiggin: Also round-robin among threads, not just cores] > Signed-off-by: Glenn Miles > --- > hw/intc/pnv_xive2.c | 18 ++++++++++++++++-- > 1 file changed, 16 insertions(+), 2 deletions(-) > > diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c > index 72cdf0f20c..d7ca97ecbb 100644 > --- a/hw/intc/pnv_xive2.c > +++ b/hw/intc/pnv_xive2.c > @@ -643,13 +643,18 @@ static int pnv_xive2_match_nvt(XivePresenter *xptr,= uint8_t format, > int i, j; > bool gen1_tima_os =3D > xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS; > + static int next_start_core; > + static int next_start_thread; > + int start_core =3D next_start_core; > + int start_thread =3D next_start_thread; > =20 > for (i =3D 0; i < chip->nr_cores; i++) { > - PnvCore *pc =3D chip->cores[i]; > + PnvCore *pc =3D chip->cores[(i + start_core) % chip->nr_cores]; > CPUCore *cc =3D CPU_CORE(pc); > =20 > for (j =3D 0; j < cc->nr_threads; j++) { > - PowerPCCPU *cpu =3D pc->threads[j]; > + /* Start search for match with different thread each call */ > + PowerPCCPU *cpu =3D pc->threads[(j + start_thread) % cc->nr_= threads]; > XiveTCTX *tctx; > int ring; > =20 > @@ -694,6 +699,15 @@ static int pnv_xive2_match_nvt(XivePresenter *xptr, = uint8_t format, > if (!match->tctx) { > match->ring =3D ring; > match->tctx =3D tctx; > + > + next_start_thread =3D j + start_thread + 1; > + if (next_start_thread >=3D cc->nr_threads) { > + next_start_thread =3D 0; > + next_start_core =3D i + start_core + 1; > + if (next_start_core >=3D chip->nr_cores) { > + next_start_core =3D 0; > + } > + } > } > count++; > }