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Thu, 15 May 2025 17:13:01 -0700 (PDT) Received: from localhost ([118.209.229.237]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-231d4af1b75sm3550085ad.85.2025.05.15.17.12.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 15 May 2025 17:13:01 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Fri, 16 May 2025 10:12:55 +1000 Message-Id: To: "Nicholas Piggin" , Cc: , =?utf-8?q?Fr=C3=A9d=C3=A9ric_Barrat?= , "Glenn Miles" , "Michael Kowal" , "Caleb Schlossin" Subject: Re: [PATCH 09/50] ppc/xive2: Fix irq preempted by lower priority group irq From: "Nicholas Piggin" X-Mailer: aerc 0.19.0 References: <20250512031100.439842-1-npiggin@gmail.com> <20250512031100.439842-10-npiggin@gmail.com> In-Reply-To: <20250512031100.439842-10-npiggin@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=npiggin@gmail.com; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon May 12, 2025 at 1:10 PM AEST, Nicholas Piggin wrote: > From: Glenn Miles > > A problem was seen where uart interrupts would be lost resulting in the > console hanging. Traces showed that a lower priority interrupt was > preempting a higher priority interrupt, which would result in the higher > priority interrupt never being handled. > > The new interrupt's priority was being compared against the CPPR > (Current Processor Priority Register) instead of the PIPR (Post > Interrupt Priority Register), as was required by the XIVE spec. > This allowed for a window between raising an interrupt and ACK'ing > the interrupt where a lower priority interrupt could slip in. > Reviewed-by: Nicholas Piggin > Fixes: 26c55b99418 ("ppc/xive2: Process group backlog when updating the C= PPR") > Signed-off-by: Glenn Miles > --- > hw/intc/xive2.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c > index 453fe37f18..2b4d0f51be 100644 > --- a/hw/intc/xive2.c > +++ b/hw/intc/xive2.c > @@ -1283,7 +1283,7 @@ bool xive2_tm_irq_precluded(XiveTCTX *tctx, int rin= g, uint8_t priority) > * priority to know if the thread can take the interrupt now or if > * it is precluded. > */ > - if (priority < alt_regs[TM_CPPR]) { > + if (priority < alt_regs[TM_PIPR]) { > return false; > } > return true;