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Thu, 15 May 2025 17:18:14 -0700 (PDT) Received: from localhost ([118.209.229.237]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-231d4edb0d0sm3353135ad.254.2025.05.15.17.18.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 15 May 2025 17:18:13 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Fri, 16 May 2025 10:18:08 +1000 Message-Id: Cc: , =?utf-8?q?Fr=C3=A9d=C3=A9ric_Barrat?= , "Glenn Miles" , "Michael Kowal" , "Caleb Schlossin" Subject: Re: [PATCH 20/50] pnv/xive2: Permit valid writes to VC/PC Flush Control registers From: "Nicholas Piggin" To: "Nicholas Piggin" , X-Mailer: aerc 0.19.0 References: <20250512031100.439842-1-npiggin@gmail.com> <20250512031100.439842-21-npiggin@gmail.com> In-Reply-To: <20250512031100.439842-21-npiggin@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=npiggin@gmail.com; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon May 12, 2025 at 1:10 PM AEST, Nicholas Piggin wrote: > From: Michael Kowal > > Writes to the Flush Control registers were logged as invalid > when they are allowed. Clearing the unsupported want_cache_disable > feature is supported, so don't log an error in that case. I guess there are no other fields in here that should be warned about attempting to set. Reviewed-by: Nicholas Piggin > > Signed-off-by: Michael Kowal > --- > hw/intc/pnv_xive2.c | 36 ++++++++++++++++++++++++++++++++---- > 1 file changed, 32 insertions(+), 4 deletions(-) > > diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c > index 3c26cd6b77..c9374f0eee 100644 > --- a/hw/intc/pnv_xive2.c > +++ b/hw/intc/pnv_xive2.c > @@ -1411,7 +1411,14 @@ static void pnv_xive2_ic_vc_write(void *opaque, hw= addr offset, > /* > * ESB cache updates (not modeled) > */ > - /* case VC_ESBC_FLUSH_CTRL: */ > + case VC_ESBC_FLUSH_CTRL: > + if (val & VC_ESBC_FLUSH_CTRL_WANT_CACHE_DISABLE) { > + xive2_error(xive, "VC: unsupported write @0x%"HWADDR_PRIx > + " value 0x%"PRIx64" bit[2] poll_want_cache_disab= le", > + offset, val); > + return; > + } > + break; > case VC_ESBC_FLUSH_POLL: > xive->vc_regs[VC_ESBC_FLUSH_CTRL >> 3] |=3D VC_ESBC_FLUSH_CTRL_P= OLL_VALID; > /* ESB update */ > @@ -1427,7 +1434,14 @@ static void pnv_xive2_ic_vc_write(void *opaque, hw= addr offset, > /* > * EAS cache updates (not modeled) > */ > - /* case VC_EASC_FLUSH_CTRL: */ > + case VC_EASC_FLUSH_CTRL: > + if (val & VC_EASC_FLUSH_CTRL_WANT_CACHE_DISABLE) { > + xive2_error(xive, "VC: unsupported write @0x%"HWADDR_PRIx > + " value 0x%"PRIx64" bit[2] poll_want_cache_disab= le", > + offset, val); > + return; > + } > + break; > case VC_EASC_FLUSH_POLL: > xive->vc_regs[VC_EASC_FLUSH_CTRL >> 3] |=3D VC_EASC_FLUSH_CTRL_P= OLL_VALID; > /* EAS update */ > @@ -1466,7 +1480,14 @@ static void pnv_xive2_ic_vc_write(void *opaque, hw= addr offset, > break; > =20 > =20 > - /* case VC_ENDC_FLUSH_CTRL: */ > + case VC_ENDC_FLUSH_CTRL: > + if (val & VC_ENDC_FLUSH_CTRL_WANT_CACHE_DISABLE) { > + xive2_error(xive, "VC: unsupported write @0x%"HWADDR_PRIx > + " value 0x%"PRIx64" bit[2] poll_want_cache_disab= le", > + offset, val); > + return; > + } > + break; > case VC_ENDC_FLUSH_POLL: > xive->vc_regs[VC_ENDC_FLUSH_CTRL >> 3] |=3D VC_ENDC_FLUSH_CTRL_P= OLL_VALID; > break; > @@ -1687,7 +1708,14 @@ static void pnv_xive2_ic_pc_write(void *opaque, hw= addr offset, > pnv_xive2_nxc_update(xive, watch_engine); > break; > =20 > - /* case PC_NXC_FLUSH_CTRL: */ > + case PC_NXC_FLUSH_CTRL: > + if (val & PC_NXC_FLUSH_CTRL_WANT_CACHE_DISABLE) { > + xive2_error(xive, "VC: unsupported write @0x%"HWADDR_PRIx > + " value 0x%"PRIx64" bit[2] poll_want_cache_disab= le", > + offset, val); > + return; > + } > + break; > case PC_NXC_FLUSH_POLL: > xive->pc_regs[PC_NXC_FLUSH_CTRL >> 3] |=3D PC_NXC_FLUSH_CTRL_POL= L_VALID; > break;