[PATCH 0/5] hw/pci-host/bonito: Improve various emulation functions

[PATCH 0/5] hw/pci-host/bonito: Improve various emulation functions

[Jiaxun Yang]

Hi all,

This series addressed a couple of missing Bonito functionalities
I found when I was trying to test NetBSD against QEMU.

Please review.

Thanks
Jiaxun

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
Jiaxun Yang (5):
      hw/pci-host/bonito: Implement ICU
      hw/pci-host/bonito: Implement PCIMAP register
      hw/pci-host/bonito: Implement DMA address translation
      hw/pci-host/bonito: Rework PCI config space accessor
      hw/pci-host/bonito: Add comments about documentation

 hw/pci-host/bonito.c     | 453 +++++++++++++++++++++++++++++------------------
 hw/pci-host/trace-events |   3 -
 2 files changed, 284 insertions(+), 172 deletions(-)
---
base-commit: c5e2c4042e3c50b96cc5eaa9683325c5a96913b0
change-id: 20250507-bonito-482759b2b52f

Best regards,
-- 
Jiaxun Yang <jiaxun.yang@flygoat.com>

[PATCH 1/5] hw/pci-host/bonito: Implement ICU

[Jiaxun Yang]

Implement interrupt controller on Bonito north bridge, as well
as PCI INTx mapping as per Fuloong 2E's hardware connection.

pci_bonito_set_irq is renamed to bonito_set_irq to reflect that
it also sets other IRQs on chip.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 hw/pci-host/bonito.c | 96 ++++++++++++++++++++++++++++++----------------------
 1 file changed, 56 insertions(+), 40 deletions(-)

diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c
index 7d6251a78d7e2e26803dd72968ca2ea7adcfe0e5..a599a1db4c068325b8c1aa8fb4a45f6b299b581b 100644
--- a/hw/pci-host/bonito.c
+++ b/hw/pci-host/bonito.c
@@ -157,6 +157,22 @@ FIELD(BONGENCFG, PCIQUEUE,      12, 1)
 #define BONITO_INTEN            (0x38 >> 2)      /* 0x138 */
 #define BONITO_INTISR           (0x3c >> 2)      /* 0x13c */
 
+/* ICU Pins */
+#define ICU_PIN_MBOXx(x)        (0 + (x))
+#define ICU_PIN_DMARDY          4
+#define ICU_PIN_DMAEMPTY        5
+#define ICU_PIN_COPYRDY         6
+#define ICU_PIN_COPYEMPTY       7
+#define ICU_PIN_COPYERR         8
+#define ICU_PIN_PCIIRQ          9
+#define ICU_PIN_MASTERERR       10
+#define ICU_PIN_SYSTEMERR       11
+#define ICU_PIN_DRAMPERR        12
+#define ICU_PIN_RETRYERR        13
+#define ICU_PIN_INTTIMER        14
+#define ICU_PIN_GPIOx(x)        (16 + (x))
+#define ICU_PIN_GPINx(x)        (25 + (x))
+
 /* PCI mail boxes */
 #define BONITO_PCIMAIL0_OFFSET    0x40
 #define BONITO_PCIMAIL1_OFFSET    0x44
@@ -206,6 +222,7 @@ struct PCIBonitoState {
 
     BonitoState *pcihost;
     uint32_t regs[BONITO_REGS];
+    uint32_t icu_pin_state;
 
     struct bonldma {
         uint32_t ldmactrl;
@@ -242,6 +259,40 @@ struct BonitoState {
 #define TYPE_PCI_BONITO "Bonito"
 OBJECT_DECLARE_SIMPLE_TYPE(PCIBonitoState, PCI_BONITO)
 
+static void bonito_update_irq(PCIBonitoState *s)
+{
+    BonitoState *bs = s->pcihost;
+    uint32_t inten = s->regs[BONITO_INTEN];
+    uint32_t intisr = s->regs[BONITO_INTISR];
+    uint32_t intpol = s->regs[BONITO_INTPOL];
+    uint32_t intedge = s->regs[BONITO_INTEDGE];
+    uint32_t pin_state = s->icu_pin_state;
+    uint32_t level, edge;
+
+    pin_state = (pin_state & ~intpol) | (~pin_state & intpol);
+
+    level = pin_state & ~intedge;
+    edge = (pin_state & ~intisr) & intedge;
+
+    intisr = (intisr & intedge) | level;
+    intisr |= edge;
+    intisr &= inten;
+
+    s->regs[BONITO_INTISR] = intisr;
+
+    qemu_set_irq(*bs->pic, !!intisr);
+}
+
+static void bonito_set_irq(void *opaque, int irq, int level)
+{
+    BonitoState *bs = opaque;
+    PCIBonitoState *s = bs->pci_dev;
+
+    s->icu_pin_state = deposit32(s->icu_pin_state, irq, 1, !!level);
+
+    bonito_update_irq(s);
+}
+
 static void bonito_writel(void *opaque, hwaddr addr,
                           uint64_t val, unsigned size)
 {
@@ -289,12 +340,12 @@ static void bonito_writel(void *opaque, hwaddr addr,
         }
         break;
     case BONITO_INTENSET:
-        s->regs[BONITO_INTENSET] = val;
         s->regs[BONITO_INTEN] |= val;
+        bonito_update_irq(s);
         break;
     case BONITO_INTENCLR:
-        s->regs[BONITO_INTENCLR] = val;
         s->regs[BONITO_INTEN] &= ~val;
+        bonito_update_irq(s);
         break;
     case BONITO_INTEN:
     case BONITO_INTISR:
@@ -549,45 +600,10 @@ static const MemoryRegionOps bonito_spciconf_ops = {
     .endianness = DEVICE_NATIVE_ENDIAN,
 };
 
-#define BONITO_IRQ_BASE 32
-
-static void pci_bonito_set_irq(void *opaque, int irq_num, int level)
-{
-    BonitoState *s = opaque;
-    qemu_irq *pic = s->pic;
-    PCIBonitoState *bonito_state = s->pci_dev;
-    int internal_irq = irq_num - BONITO_IRQ_BASE;
-
-    if (bonito_state->regs[BONITO_INTEDGE] & (1 << internal_irq)) {
-        qemu_irq_pulse(*pic);
-    } else {   /* level triggered */
-        if (bonito_state->regs[BONITO_INTPOL] & (1 << internal_irq)) {
-            qemu_irq_raise(*pic);
-        } else {
-            qemu_irq_lower(*pic);
-        }
-    }
-}
-
-/* map the original irq (0~3) to bonito irq (16~47, but 16~31 are unused) */
 static int pci_bonito_map_irq(PCIDevice *pci_dev, int irq_num)
 {
-    int slot;
-
-    slot = PCI_SLOT(pci_dev->devfn);
-
-    switch (slot) {
-    case 5:   /* FULOONG2E_VIA_SLOT, SouthBridge, IDE, USB, ACPI, AC97, MC97 */
-        return irq_num % 4 + BONITO_IRQ_BASE;
-    case 6:   /* FULOONG2E_ATI_SLOT, VGA */
-        return 4 + BONITO_IRQ_BASE;
-    case 7:   /* FULOONG2E_RTL_SLOT, RTL8139 */
-        return 5 + BONITO_IRQ_BASE;
-    case 8 ... 12: /* PCI slot 1 to 4 */
-        return (slot - 8 + irq_num) + 6 + BONITO_IRQ_BASE;
-    default:  /* Unknown device, don't do any translation */
-        return irq_num;
-    }
+    /* Fuloong 2E PCI INTX are connected to Bonito GPIN[3:0] */
+    return ICU_PIN_GPINx(irq_num);
 }
 
 static void bonito_reset_hold(Object *obj, ResetType type)
@@ -633,7 +649,7 @@ static void bonito_host_realize(DeviceState *dev, Error **errp)
 
     memory_region_init(&bs->pci_mem, OBJECT(dev), "pci.mem", BONITO_PCIHI_SIZE);
     phb->bus = pci_register_root_bus(dev, "pci",
-                                     pci_bonito_set_irq, pci_bonito_map_irq,
+                                     bonito_set_irq, pci_bonito_map_irq,
                                      dev, &bs->pci_mem, get_system_io(),
                                      PCI_DEVFN(5, 0), 32, TYPE_PCI_BUS);
 

-- 
Git-154)

[PATCH 2/5] hw/pci-host/bonito: Implement PCIMAP register

[Jiaxun Yang]

PCIMAP controls how PCILO and PCIHi regions map into
PCI memory space.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 hw/pci-host/bonito.c | 37 ++++++++++++++++++++++++++++++++-----
 1 file changed, 32 insertions(+), 5 deletions(-)

diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c
index a599a1db4c068325b8c1aa8fb4a45f6b299b581b..f509f22df90ff7ed31ff5387a0acc239c22fd5f6 100644
--- a/hw/pci-host/bonito.c
+++ b/hw/pci-host/bonito.c
@@ -137,6 +137,12 @@ FIELD(BONGENCFG, PCIQUEUE,      12, 1)
 
 /* 4. PCI address map control */
 #define BONITO_PCIMAP           (0x10 >> 2)      /* 0x110 */
+REG32(PCIMAP,        0x110)
+FIELD(PCIMAP, LO0, 0, 6)
+FIELD(PCIMAP, LO1, 6, 6)
+FIELD(PCIMAP, LO2, 12, 6)
+FIELD(PCIMAP, 2, 18, 1)
+
 #define BONITO_PCIMEMBASECFG    (0x14 >> 2)      /* 0x114 */
 #define BONITO_PCIMAP_CFG       (0x18 >> 2)      /* 0x118 */
 
@@ -245,7 +251,6 @@ struct PCIBonitoState {
     MemoryRegion iomem_cop;
     MemoryRegion bonito_pciio;
     MemoryRegion bonito_localio;
-
 };
 typedef struct PCIBonitoState PCIBonitoState;
 
@@ -254,6 +259,8 @@ struct BonitoState {
     qemu_irq *pic;
     PCIBonitoState *pci_dev;
     MemoryRegion pci_mem;
+    MemoryRegion *pcimem_lo_alias;
+    MemoryRegion *pcimem_hi_alias;
 };
 
 #define TYPE_PCI_BONITO "Bonito"
@@ -293,6 +300,20 @@ static void bonito_set_irq(void *opaque, int irq, int level)
     bonito_update_irq(s);
 }
 
+static void bonito_update_pcimap(PCIBonitoState *s)
+{
+    uint32_t pcimap = s->regs[BONITO_PCIMAP];
+
+    memory_region_set_alias_offset(&s->pcihost->pcimem_lo_alias[0],
+                                   FIELD_EX32(pcimap, PCIMAP, LO0) << 26);
+    memory_region_set_alias_offset(&s->pcihost->pcimem_lo_alias[1],
+                                   FIELD_EX32(pcimap, PCIMAP, LO1) << 26);
+    memory_region_set_alias_offset(&s->pcihost->pcimem_lo_alias[2],
+                                   FIELD_EX32(pcimap, PCIMAP, LO2) << 26);
+    memory_region_set_alias_offset(s->pcihost->pcimem_hi_alias,
+                                   FIELD_EX32(pcimap, PCIMAP, 2) << 31);
+}
+
 static void bonito_writel(void *opaque, hwaddr addr,
                           uint64_t val, unsigned size)
 {
@@ -308,7 +329,6 @@ static void bonito_writel(void *opaque, hwaddr addr,
     case BONITO_BONPONCFG:
     case BONITO_IODEVCFG:
     case BONITO_SDCFG:
-    case BONITO_PCIMAP:
     case BONITO_PCIMEMBASECFG:
     case BONITO_PCIMAP_CFG:
     case BONITO_GPIODATA:
@@ -330,6 +350,10 @@ static void bonito_writel(void *opaque, hwaddr addr,
     case BONITO_MEMSIZE:
         s->regs[saddr] = val;
         break;
+    case BONITO_PCIMAP:
+        s->regs[BONITO_PCIMAP] = val;
+        bonito_update_pcimap(s);
+        break;
     case BONITO_BONGENCFG:
         if (!(s->regs[saddr] & 0x04) && (val & 0x04)) {
             reset = 1; /* bit 2 jump from 0 to 1 cause reset */
@@ -664,6 +688,8 @@ static void bonito_host_realize(DeviceState *dev, Error **errp)
         g_free(name);
     }
 
+    bs->pcimem_lo_alias = pcimem_lo_alias;
+
     create_unimplemented_device("pci.io", BONITO_PCIIO_BASE, 1 * MiB);
 }
 
@@ -673,7 +699,7 @@ static void bonito_pci_realize(PCIDevice *dev, Error **errp)
     MemoryRegion *host_mem = get_system_memory();
     PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
     BonitoState *bs = s->pcihost;
-    MemoryRegion *pcimem_alias = g_new(MemoryRegion, 1);
+    MemoryRegion *pcimem_hi_alias = g_new(MemoryRegion, 1);
 
     /*
      * Bonito North Bridge, built on FPGA,
@@ -730,9 +756,10 @@ static void bonito_pci_realize(PCIDevice *dev, Error **errp)
     create_unimplemented_device("IOCS[3]", BONITO_DEV_BASE + 3 * 256 * KiB,
                                 256 * KiB);
 
-    memory_region_init_alias(pcimem_alias, NULL, "pci.mem.alias",
+    memory_region_init_alias(pcimem_hi_alias, NULL, "pci.memhi.alias",
                              &bs->pci_mem, 0, BONITO_PCIHI_SIZE);
-    memory_region_add_subregion(host_mem, BONITO_PCIHI_BASE, pcimem_alias);
+    memory_region_add_subregion(host_mem, BONITO_PCIHI_BASE, pcimem_hi_alias);
+    bs->pcimem_hi_alias = pcimem_hi_alias;
     create_unimplemented_device("PCI_2",
                                 (hwaddr)BONITO_PCIHI_BASE + BONITO_PCIHI_SIZE,
                                 2 * GiB);

-- 
Git-154)

[PATCH 3/5] hw/pci-host/bonito: Implement DMA address translation

[Jiaxun Yang]

PCIBase (Host Bridge config space BARs) and PCIBaseCfg registers
in Bonito controls PCI DMA address translation.

For any incoming DMA requests, it will be matched against PCiBase{0, 1}
together with PciBaseCfg.MASK{0,1}. If it hits any of both, higher bits
of address will be replaced by PciBaseCfg.TRANSx.

Emulating this behavior by PCI IOMMU DMA address space with dynamic
remapping on register writes.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 hw/pci-host/bonito.c | 113 +++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 113 insertions(+)

diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c
index f509f22df90ff7ed31ff5387a0acc239c22fd5f6..1c0d502a1e2dfa3c9803ca219cf505e08bf94a75 100644
--- a/hw/pci-host/bonito.c
+++ b/hw/pci-host/bonito.c
@@ -144,6 +144,17 @@ FIELD(PCIMAP, LO2, 12, 6)
 FIELD(PCIMAP, 2, 18, 1)
 
 #define BONITO_PCIMEMBASECFG    (0x14 >> 2)      /* 0x114 */
+REG32(PCIMEMBASECFG, 0x114)
+FIELD(PCIMEMBASECFG, MASK0, 0, 5)
+FIELD(PCIMEMBASECFG, TRANS0, 5, 5)
+FIELD(PCIMEMBASECFG, CACHED0, 10, 1)
+FIELD(PCIMEMBASECFG, IO0, 11, 1)
+FIELD(PCIMEMBASECFG, MASK1, 12, 5)
+FIELD(PCIMEMBASECFG, TRANS1, 17, 5)
+FIELD(PCIMEMBASECFG, CACHED1, 22, 1)
+FIELD(PCIMEMBASECFG, IO1, 23, 1)
+
+
 #define BONITO_PCIMAP_CFG       (0x18 >> 2)      /* 0x118 */
 
 /* 5. ICU & GPIO regs */
@@ -258,9 +269,12 @@ struct BonitoState {
     PCIHostState parent_obj;
     qemu_irq *pic;
     PCIBonitoState *pci_dev;
+    MemoryRegion dma_mr;
     MemoryRegion pci_mem;
+    AddressSpace dma_as;
     MemoryRegion *pcimem_lo_alias;
     MemoryRegion *pcimem_hi_alias;
+    MemoryRegion *dma_alias;
 };
 
 #define TYPE_PCI_BONITO "Bonito"
@@ -314,6 +328,57 @@ static void bonito_update_pcimap(PCIBonitoState *s)
                                    FIELD_EX32(pcimap, PCIMAP, 2) << 31);
 }
 
+static void pcibasecfg_decode(uint32_t mask, uint32_t trans, bool io,
+                                     uint32_t *base, uint32_t *size)
+{
+    uint32_t val;
+
+    mask = (mask << 23 | 0xF0000000);
+    val = ctz32(mask);
+    *size = 1 << val;
+    *base = (trans & ~(*size - 1)) | io << 28;
+}
+
+static void bonito_update_pcibase(PCIBonitoState *s)
+{
+    uint32_t pcibasecfg = s->regs[BONITO_PCIMEMBASECFG];
+    uint32_t size, base;
+    uint32_t pcibase, wmask;
+
+    pcibasecfg_decode(FIELD_EX32(pcibasecfg, PCIMEMBASECFG, MASK0),
+                      FIELD_EX32(pcibasecfg, PCIMEMBASECFG, TRANS0),
+                      FIELD_EX32(pcibasecfg, PCIMEMBASECFG, IO0),
+                      &base, &size);
+
+    wmask = ~(size - 1);
+    /* Mask will also influence PCIBase register writable range */
+    pci_set_long(s->dev.wmask + PCI_BASE_ADDRESS_0, wmask);
+    /* Clear RO bits in PCIBase */
+    pcibase = pci_get_long(s->dev.config + PCI_BASE_ADDRESS_0);
+    pcibase &= wmask;
+    pci_set_long(s->dev.config + PCI_BASE_ADDRESS_0, pcibase);
+    /* Adjust DMA spaces */
+    memory_region_set_size(&s->pcihost->dma_alias[0], size);
+    memory_region_set_alias_offset(&s->pcihost->dma_alias[0], base);
+    memory_region_set_address(&s->pcihost->dma_alias[0], pcibase);
+
+    /* Ditto for PCIMEMBASECFG1 */
+    pcibasecfg_decode(FIELD_EX32(pcibasecfg, PCIMEMBASECFG, MASK1),
+                      FIELD_EX32(pcibasecfg, PCIMEMBASECFG, TRANS1),
+                      FIELD_EX32(pcibasecfg, PCIMEMBASECFG, IO1),
+                      &base, &size);
+
+    wmask = ~(size - 1);
+    pci_set_long(s->dev.wmask + PCI_BASE_ADDRESS_1, wmask);
+    pcibase = pci_get_long(s->dev.config + PCI_BASE_ADDRESS_1);
+    pcibase &= wmask;
+    pci_set_long(s->dev.config + PCI_BASE_ADDRESS_1, pcibase);
+
+    memory_region_set_size(&s->pcihost->dma_alias[1], size);
+    memory_region_set_alias_offset(&s->pcihost->dma_alias[1], base);
+    memory_region_set_address(&s->pcihost->dma_alias[1], pcibase);
+}
+
 static void bonito_writel(void *opaque, hwaddr addr,
                           uint64_t val, unsigned size)
 {
@@ -624,12 +689,35 @@ static const MemoryRegionOps bonito_spciconf_ops = {
     .endianness = DEVICE_NATIVE_ENDIAN,
 };
 
+static void bonito_pci_write_config(PCIDevice *dev, uint32_t address,
+                                    uint32_t val, int len)
+{
+    pci_default_write_config(dev, address, val, len);
+
+    if (ranges_overlap(address, len, PCI_BASE_ADDRESS_0, 12)) {
+        /* Bonito Host Bridge BARs are defined as DMA windows (pciBase) */
+        bonito_update_pcibase(PCI_BONITO(dev));
+    }
+}
+
 static int pci_bonito_map_irq(PCIDevice *pci_dev, int irq_num)
 {
     /* Fuloong 2E PCI INTX are connected to Bonito GPIN[3:0] */
     return ICU_PIN_GPINx(irq_num);
 }
 
+static AddressSpace *bonito_pcihost_set_iommu(PCIBus *bus, void *opaque,
+                                              int devfn)
+{
+    BonitoState *bs = opaque;
+
+    return &bs->dma_as;
+}
+
+static const PCIIOMMUOps bonito_iommu_ops = {
+    .get_address_space = bonito_pcihost_set_iommu,
+};
+
 static void bonito_reset_hold(Object *obj, ResetType type)
 {
     PCIBonitoState *s = PCI_BONITO(obj);
@@ -653,6 +741,11 @@ static void bonito_reset_hold(Object *obj, ResetType type)
     s->regs[BONITO_DQCFG] = 0x8;
     s->regs[BONITO_MEMSIZE] = 0x10000000;
     s->regs[BONITO_PCIMAP] = 0x6140;
+    bonito_update_pcimap(s);
+
+    pci_set_long(s->dev.config + PCI_BASE_ADDRESS_0, 0x80000000);
+    pci_set_long(s->dev.config + PCI_BASE_ADDRESS_1, 0x0);
+    bonito_update_pcibase(s);
 }
 
 static const VMStateDescription vmstate_bonito = {
@@ -700,6 +793,7 @@ static void bonito_pci_realize(PCIDevice *dev, Error **errp)
     PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
     BonitoState *bs = s->pcihost;
     MemoryRegion *pcimem_hi_alias = g_new(MemoryRegion, 1);
+    MemoryRegion *dma_alias = g_new(MemoryRegion, 2);
 
     /*
      * Bonito North Bridge, built on FPGA,
@@ -764,6 +858,24 @@ static void bonito_pci_realize(PCIDevice *dev, Error **errp)
                                 (hwaddr)BONITO_PCIHI_BASE + BONITO_PCIHI_SIZE,
                                 2 * GiB);
 
+    /* 32bit DMA */
+    memory_region_init(&bs->dma_mr, OBJECT(s), "dma.pciBase", 4 * GiB);
+
+    /* pciBase0, mapped to system RAM */
+    memory_region_init_alias(&dma_alias[0], NULL, "pciBase0.mem.alias",
+                             host_mem, 0x80000000, 256 * MiB);
+    memory_region_add_subregion_overlap(&bs->dma_mr, 0, &dma_alias[0], 2);
+
+    /* pciBase1, mapped to system RAM */
+    memory_region_init_alias(&dma_alias[1], NULL, "pciBase1.mem.alias",
+                            host_mem, 0, 256 * MiB);
+    memory_region_add_subregion_overlap(&bs->dma_mr, 0, &dma_alias[1], 1);
+
+    bs->dma_alias = dma_alias;
+
+    address_space_init(&bs->dma_as, &bs->dma_mr, "pciBase.dma");
+    pci_setup_iommu(phb->bus, &bonito_iommu_ops, bs);
+
     /* set the default value of north bridge pci config */
     pci_set_word(dev->config + PCI_COMMAND, 0x0000);
     pci_set_word(dev->config + PCI_STATUS, 0x0000);
@@ -806,6 +918,7 @@ static void bonito_pci_class_init(ObjectClass *klass, const void *data)
     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
     ResettableClass *rc = RESETTABLE_CLASS(klass);
 
+    k->config_write = bonito_pci_write_config;
     rc->phases.hold = bonito_reset_hold;
     k->realize = bonito_pci_realize;
     k->vendor_id = 0xdf53;

-- 
Git-154)

[PATCH 4/5] hw/pci-host/bonito: Rework PCI config space accessor

[Jiaxun Yang]

The original PCI config space accessor failed to issue master abort
interrupt as necessary, it also didn't handle type 1 access and
using south bridge concept which doesn't exist in Bonito.

Rework the whole mechanism accorading to the manual, also remove
inaccurate comments.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 hw/pci-host/bonito.c     | 202 ++++++++++++++++++-----------------------------
 hw/pci-host/trace-events |   3 -
 2 files changed, 75 insertions(+), 130 deletions(-)

diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c
index 1c0d502a1e2dfa3c9803ca219cf505e08bf94a75..49b4be26393a08eda4f99c8e2ef8a0c455c57bc0 100644
--- a/hw/pci-host/bonito.c
+++ b/hw/pci-host/bonito.c
@@ -14,30 +14,6 @@
  * fuloong 2e mini pc has a bonito north bridge.
  */
 
-/*
- * what is the meaning of devfn in qemu and IDSEL in bonito northbridge?
- *
- * devfn   pci_slot<<3  + funno
- * one pci bus can have 32 devices and each device can have 8 functions.
- *
- * In bonito north bridge, pci slot = IDSEL bit - 12.
- * For example, PCI_IDSEL_VIA686B = 17,
- * pci slot = 17-12=5
- *
- * so
- * VT686B_FUN0's devfn = (5<<3)+0
- * VT686B_FUN1's devfn = (5<<3)+1
- *
- * qemu also uses pci address for north bridge to access pci config register.
- * bus_no   [23:16]
- * dev_no   [15:11]
- * fun_no   [10:8]
- * reg_no   [7:2]
- *
- * so function bonito_sbridge_pciaddr for the translation from
- * north bridge address to pci address.
- */
-
 #include "qemu/osdep.h"
 #include "qemu/units.h"
 #include "qapi/error.h"
@@ -106,11 +82,6 @@
 #define BONITO_INTERNAL_REG_BASE  (BONITO_REGBASE + BONITO_REG_BASE)
 #define BONITO_INTERNAL_REG_SIZE  (0x70)
 
-#define BONITO_SPCICONFIG_BASE  (BONITO_PCICFG_BASE)
-#define BONITO_SPCICONFIG_SIZE  (BONITO_PCICFG_SIZE)
-
-
-
 /* 1. Bonito h/w Configuration */
 /* Power on register */
 
@@ -156,6 +127,9 @@ FIELD(PCIMEMBASECFG, IO1, 23, 1)
 
 
 #define BONITO_PCIMAP_CFG       (0x18 >> 2)      /* 0x118 */
+REG32(PCIMAP_CFG,    0x118)
+FIELD(PCIMAP_CFG, AD16UP, 0, 16)
+FIELD(PCIMAP_CFG, TYPE1, 16, 1)
 
 /* 5. ICU & GPIO regs */
 /* GPIO Regs - r/w */
@@ -214,23 +188,14 @@ FIELD(PCIMEMBASECFG, IO1, 23, 1)
 
 #define BONITO_REGS             (0x70 >> 2)
 
-/* PCI config for south bridge. type 0 */
-#define BONITO_PCICONF_IDSEL_MASK      0xfffff800     /* [31:11] */
-#define BONITO_PCICONF_IDSEL_OFFSET    11
-#define BONITO_PCICONF_FUN_MASK        0x700    /* [10:8] */
-#define BONITO_PCICONF_FUN_OFFSET      8
-#define BONITO_PCICONF_REG_MASK_DS     (~3)         /* Per datasheet */
-#define BONITO_PCICONF_REG_MASK_HW     0xff         /* As seen running PMON */
-#define BONITO_PCICONF_REG_OFFSET      0
-
+/* PCI Access Cycle Fields */
+FIELD(TYPE0_CYCLE, FUNC, 8, 3)
+FIELD(TYPE0_CYCLE, IDSEL, 11, 21)
 
-/* idsel BIT = pci slot number +12 */
-#define PCI_SLOT_BASE              12
-#define PCI_IDSEL_VIA686B_BIT      (17)
-#define PCI_IDSEL_VIA686B          (1 << PCI_IDSEL_VIA686B_BIT)
-
-#define PCI_ADDR(busno , devno , funno , regno)  \
-    ((PCI_BUILD_BDF(busno, PCI_DEVFN(devno , funno)) << 8) + (regno))
+FIELD(TYPE1_CYCLE, FUNC, 8, 3)
+FIELD(TYPE1_CYCLE, DEV, 11, 5)
+FIELD(TYPE1_CYCLE, BUS, 16, 8)
+FIELD(TYPE1_CYCLE, IDSEL, 24, 8)
 
 typedef struct BonitoState BonitoState;
 
@@ -580,108 +545,91 @@ static const MemoryRegionOps bonito_cop_ops = {
     },
 };
 
-static uint32_t bonito_sbridge_pciaddr(void *opaque, hwaddr addr)
+static PCIDevice *bonito_pcihost_cfg_decode(PCIBonitoState *s, hwaddr addr)
 {
-    PCIBonitoState *s = opaque;
     PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
-    uint32_t cfgaddr;
-    uint32_t idsel;
-    uint32_t devno;
-    uint32_t funno;
-    uint32_t regno;
-    uint32_t pciaddr;
-
-    /* support type0 pci config */
-    if ((s->regs[BONITO_PCIMAP_CFG] & 0x10000) != 0x0) {
-        return 0xffffffff;
+    uint32_t pcimap_cfg = s->regs[BONITO_PCIMAP_CFG];
+    uint32_t cycle, dev, func, bus;
+
+    cycle = addr | FIELD_EX32(pcimap_cfg, PCIMAP_CFG, AD16UP) << 16;
+
+    if (FIELD_EX32(pcimap_cfg, PCIMAP_CFG, TYPE1)) {
+        dev = FIELD_EX32(cycle, TYPE1_CYCLE, DEV);
+        func = FIELD_EX32(cycle, TYPE1_CYCLE, FUNC);
+        bus = FIELD_EX32(cycle, TYPE1_CYCLE, BUS);
+    } else {
+        uint32_t idsel = FIELD_EX32(cycle, TYPE0_CYCLE, IDSEL);
+        if (idsel == 0) {
+            return NULL;
+        }
+        dev = ctz32(idsel);
+        func = FIELD_EX32(cycle, TYPE0_CYCLE, FUNC);
+        bus = 0;
     }
 
-    cfgaddr = addr & 0xffff;
-    cfgaddr |= (s->regs[BONITO_PCIMAP_CFG] & 0xffff) << 16;
+    return pci_find_device(phb->bus, bus, PCI_DEVFN(dev, func));
+}
 
-    idsel = (cfgaddr & BONITO_PCICONF_IDSEL_MASK) >>
-             BONITO_PCICONF_IDSEL_OFFSET;
-    devno = ctz32(idsel);
-    funno = (cfgaddr & BONITO_PCICONF_FUN_MASK) >> BONITO_PCICONF_FUN_OFFSET;
-    regno = (cfgaddr & BONITO_PCICONF_REG_MASK_HW) >> BONITO_PCICONF_REG_OFFSET;
+static void bonito_pcihost_signal_mabort(PCIBonitoState *s)
+{
+    PCIDevice *d = &s->dev;
+    uint16_t status = pci_get_word(d->config + PCI_STATUS);
 
-    if (idsel == 0) {
-        error_report("error in bonito pci config address 0x" HWADDR_FMT_plx
-                     ",pcimap_cfg=0x%x", addr, s->regs[BONITO_PCIMAP_CFG]);
-        exit(1);
-    }
-    pciaddr = PCI_ADDR(pci_bus_num(phb->bus), devno, funno, regno);
-    DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d\n",
-        cfgaddr, pciaddr, pci_bus_num(phb->bus), devno, funno, regno);
+    status |= PCI_STATUS_REC_MASTER_ABORT;
+    pci_set_word(d->config + PCI_STATUS, status);
 
-    return pciaddr;
+    /* Generate a pulse, it's a edge triggered IRQ */
+    bonito_set_irq(s->pcihost, ICU_PIN_MASTERERR, 1);
+    bonito_set_irq(s->pcihost, ICU_PIN_MASTERERR, 0);
 }
 
-static void bonito_spciconf_write(void *opaque, hwaddr addr, uint64_t val,
-                                  unsigned size)
+static MemTxResult bonito_pcihost_cfg_read(void *opaque, hwaddr addr,
+                                           uint64_t *data, unsigned len,
+                                           MemTxAttrs attrs)
 {
     PCIBonitoState *s = opaque;
-    PCIDevice *d = PCI_DEVICE(s);
-    PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
-    uint32_t pciaddr;
-    uint16_t status;
-
-    DPRINTF("bonito_spciconf_write "HWADDR_FMT_plx" size %d val %lx\n",
-            addr, size, val);
-
-    pciaddr = bonito_sbridge_pciaddr(s, addr);
-
-    if (pciaddr == 0xffffffff) {
-        return;
-    }
-    if (addr & ~BONITO_PCICONF_REG_MASK_DS) {
-        trace_bonito_spciconf_small_access(addr, size);
+    PCIDevice *dev;
+
+    dev = bonito_pcihost_cfg_decode(s, addr);
+    if (!dev) {
+        bonito_pcihost_signal_mabort(s);
+        /*
+         * Vanilla bonito will actually triiger a bus error on master abort,
+         * Godson variant won't. We need to return all 1s.
+         */
+        *data = UINT64_MAX;
+        return MEMTX_OK;
     }
 
-    /* set the pci address in s->config_reg */
-    phb->config_reg = (pciaddr) | (1u << 31);
-    pci_data_write(phb->bus, phb->config_reg, val, size);
+    addr &= PCI_CONFIG_SPACE_SIZE - 1;
+    *data = pci_host_config_read_common(dev, addr, pci_config_size(dev), len);
 
-    /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
-    status = pci_get_word(d->config + PCI_STATUS);
-    status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
-    pci_set_word(d->config + PCI_STATUS, status);
+    return MEMTX_OK;
 }
 
-static uint64_t bonito_spciconf_read(void *opaque, hwaddr addr, unsigned size)
+static MemTxResult bonito_pcihost_cfg_write(void *opaque, hwaddr addr,
+                                            uint64_t data, unsigned len,
+                                            MemTxAttrs attrs)
 {
     PCIBonitoState *s = opaque;
-    PCIDevice *d = PCI_DEVICE(s);
-    PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
-    uint32_t pciaddr;
-    uint16_t status;
-
-    DPRINTF("bonito_spciconf_read "HWADDR_FMT_plx" size %d\n", addr, size);
+    PCIDevice *dev;
 
-    pciaddr = bonito_sbridge_pciaddr(s, addr);
-
-    if (pciaddr == 0xffffffff) {
-        return MAKE_64BIT_MASK(0, size * 8);
-    }
-    if (addr & ~BONITO_PCICONF_REG_MASK_DS) {
-        trace_bonito_spciconf_small_access(addr, size);
+    dev = bonito_pcihost_cfg_decode(s, addr);
+    if (!dev) {
+        bonito_pcihost_signal_mabort(s);
+        return MEMTX_OK;
     }
 
-    /* set the pci address in s->config_reg */
-    phb->config_reg = (pciaddr) | (1u << 31);
-
-    /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
-    status = pci_get_word(d->config + PCI_STATUS);
-    status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
-    pci_set_word(d->config + PCI_STATUS, status);
+    addr &= PCI_CONFIG_SPACE_SIZE - 1;
+    pci_host_config_write_common(dev, addr, pci_config_size(dev), data, len);
 
-    return pci_data_read(phb->bus, phb->config_reg, size);
+    return MEMTX_OK;
 }
 
-/* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */
-static const MemoryRegionOps bonito_spciconf_ops = {
-    .read = bonito_spciconf_read,
-    .write = bonito_spciconf_write,
+/* PCI Configure Space access region. 0x1fe8 0000 - 0x1fef ffff */
+static const MemoryRegionOps bonito_pcihost_cfg_ops = {
+    .read_with_attrs = bonito_pcihost_cfg_read,
+    .write_with_attrs = bonito_pcihost_cfg_write,
     .valid.min_access_size = 1,
     .valid.max_access_size = 4,
     .impl.min_access_size = 1,
@@ -812,10 +760,10 @@ static void bonito_pci_realize(PCIDevice *dev, Error **errp)
     memory_region_add_subregion(host_mem, BONITO_PCICONFIG_BASE,
                                 &phb->conf_mem);
 
-    /* set the south bridge pci configure  mapping */
-    memory_region_init_io(&phb->data_mem, OBJECT(s), &bonito_spciconf_ops, s,
-                          "south-bridge-pci-config", BONITO_SPCICONFIG_SIZE);
-    memory_region_add_subregion(host_mem, BONITO_SPCICONFIG_BASE,
+    /* set the pci config space accessor mapping */
+    memory_region_init_io(&phb->data_mem, OBJECT(s), &bonito_pcihost_cfg_ops, s,
+                          "pci-host-config-access", BONITO_PCICFG_SIZE);
+    memory_region_add_subregion(host_mem, BONITO_PCICFG_BASE,
                                 &phb->data_mem);
 
     create_unimplemented_device("bonito", BONITO_REG_BASE, BONITO_REG_SIZE);
diff --git a/hw/pci-host/trace-events b/hw/pci-host/trace-events
index 0a816b9aa129bb0c37d207e2612e09ac4762d51a..bd9bdeadfd3678e303a412688d689cc01d06f709 100644
--- a/hw/pci-host/trace-events
+++ b/hw/pci-host/trace-events
@@ -1,8 +1,5 @@
 # See docs/devel/tracing.rst for syntax documentation.
 
-# bonito.c
-bonito_spciconf_small_access(uint64_t addr, unsigned size) "PCI config address is smaller then 32-bit, addr: 0x%"PRIx64", size: %u"
-
 # grackle.c
 grackle_set_irq(int irq_num, int level) "set_irq num %d level %d"
 

-- 
Git-154)

[PATCH 5/5] hw/pci-host/bonito: Add comments about documentation

[Jiaxun Yang]

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 hw/pci-host/bonito.c | 21 ++++++++++++++++-----
 1 file changed, 16 insertions(+), 5 deletions(-)

diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c
index 49b4be26393a08eda4f99c8e2ef8a0c455c57bc0..918ee39661004d902d2deb25dd5e782855a11854 100644
--- a/hw/pci-host/bonito.c
+++ b/hw/pci-host/bonito.c
@@ -1,5 +1,5 @@
 /*
- * bonito north bridge support
+ * Algorithmics Ltd BONITO north bridge emulation
  *
  * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
  * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
@@ -8,10 +8,21 @@
  *
  * Contributions after 2012-01-13 are licensed under the terms of the
  * GNU GPL, version 2 or (at your option) any later version.
- */
-
-/*
- * fuloong 2e mini pc has a bonito north bridge.
+ *
+ * For 32-bit variant:
+ * "BONITO - PCI/SDRAM System Controller for Vr43xx"
+ * https://wiki.qemu.org/File:Bonito-spec.pdf
+ *
+ * "BONITO - Companion Chip for Vr43xx and Vr5xxx" (uPD65949S1-P00-F6)
+ * https://repo.oss.cipunited.com/archives/docs/NEC/U15789EE1V0DS00.pdf
+ *
+ * For 64-bit variant:
+ * "BONITO64 - "north bridge" controller for 64-bit MIPS CPUs"
+ * https://wiki.qemu.org/File:Bonito-spec.pdf
+ *
+ * For Godson (Loongson) 2E variant:
+ * "Godson 2E North Bridge User Manual" (in Chinese)
+ * https://github.com/loongson-community/docs/blob/master/2E/Godson_2E_NB_UM.pdf
  */
 
 #include "qemu/osdep.h"

-- 
Git-154)

Re: [PATCH 0/5] hw/pci-host/bonito: Improve various emulation functions

[Jiaxun Yang]

在2025年5月8日周四 下午3:46，Jiaxun Yang写道：
> Hi all,
>
> This series addressed a couple of missing Bonito functionalities
> I found when I was trying to test NetBSD against QEMU.

Hi Philippe,

A gentle ping :-)

Do you have bandwidth on MIPS recently?

I'm planning to respin my CPS SMP series as well.

Thanks
Jiaxun

>
> Please review.
>
> Thanks
> Jiaxun
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
> Jiaxun Yang (5):
>       hw/pci-host/bonito: Implement ICU
>       hw/pci-host/bonito: Implement PCIMAP register
>       hw/pci-host/bonito: Implement DMA address translation
>       hw/pci-host/bonito: Rework PCI config space accessor
>       hw/pci-host/bonito: Add comments about documentation
>
>  hw/pci-host/bonito.c     | 453 +++++++++++++++++++++++++++++------------------
>  hw/pci-host/trace-events |   3 -
>  2 files changed, 284 insertions(+), 172 deletions(-)
> ---
> base-commit: c5e2c4042e3c50b96cc5eaa9683325c5a96913b0
> change-id: 20250507-bonito-482759b2b52f
>
> Best regards,
> -- 
> Jiaxun Yang <jiaxun.yang@flygoat.com>

-- 
- Jiaxun

Re: [PATCH 0/5] hw/pci-host/bonito: Improve various emulation functions

[Jiaxun Yang]

在2025年5月8日周四 下午3:46，Jiaxun Yang写道：
> Hi all,
>
> This series addressed a couple of missing Bonito functionalities
> I found when I was trying to test NetBSD against QEMU.
>
> Please review.

Another ping :-)

Thanks
Jiaxun

>
> Thanks
> Jiaxun
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
> Jiaxun Yang (5):
>       hw/pci-host/bonito: Implement ICU
>       hw/pci-host/bonito: Implement PCIMAP register
>       hw/pci-host/bonito: Implement DMA address translation
>       hw/pci-host/bonito: Rework PCI config space accessor
>       hw/pci-host/bonito: Add comments about documentation
>
>  hw/pci-host/bonito.c     | 453 +++++++++++++++++++++++++++++------------------
>  hw/pci-host/trace-events |   3 -
>  2 files changed, 284 insertions(+), 172 deletions(-)
> ---
> base-commit: c5e2c4042e3c50b96cc5eaa9683325c5a96913b0
> change-id: 20250507-bonito-482759b2b52f
>
> Best regards,
> -- 
> Jiaxun Yang <jiaxun.yang@flygoat.com>

-- 
- Jiaxun

Re: [PATCH 0/5] hw/pci-host/bonito: Improve various emulation functions

[Jiaxun Yang]

在2025年7月16日周三 上午3:09，Jiaxun Yang写道：
> 在2025年5月8日周四 下午3:46，Jiaxun Yang写道：
>> Hi all,
>>
>> This series addressed a couple of missing Bonito functionalities
>> I found when I was trying to test NetBSD against QEMU.
>>
>> Please review.
>
> Another ping :-)

Ping :-)

>
> Thanks
> Jiaxun
>
>>
>> Thanks
>> Jiaxun
>>
>> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>> ---
>> Jiaxun Yang (5):
>>       hw/pci-host/bonito: Implement ICU
>>       hw/pci-host/bonito: Implement PCIMAP register
>>       hw/pci-host/bonito: Implement DMA address translation
>>       hw/pci-host/bonito: Rework PCI config space accessor
>>       hw/pci-host/bonito: Add comments about documentation
>>
>>  hw/pci-host/bonito.c     | 453 +++++++++++++++++++++++++++++------------------
>>  hw/pci-host/trace-events |   3 -
>>  2 files changed, 284 insertions(+), 172 deletions(-)
>> ---
>> base-commit: c5e2c4042e3c50b96cc5eaa9683325c5a96913b0
>> change-id: 20250507-bonito-482759b2b52f
>>
>> Best regards,
>> -- 
>> Jiaxun Yang <jiaxun.yang@flygoat.com>
>
> -- 
> - Jiaxun

-- 
- Jiaxun

Re: [PATCH 0/5] hw/pci-host/bonito: Improve various emulation functions

[Bernhard Beschow]

Am 3. September 2025 05:34:18 UTC schrieb Jiaxun Yang <jiaxun.yang@flygoat.com>:
>
>
>在2025年7月16日周三 上午3:09，Jiaxun Yang写道：
>> 在2025年5月8日周四 下午3:46，Jiaxun Yang写道：
>>> Hi all,
>>>
>>> This series addressed a couple of missing Bonito functionalities
>>> I found when I was trying to test NetBSD against QEMU.
>>>
>>> Please review.
>>
>> Another ping :-)
>
>Ping :-)

Maybe we can then also apply https://lore.kernel.org/qemu-devel/20230105154440.259361-1-shentey@gmail.com ?

Best regards,
Bernhard

>
>>
>> Thanks
>> Jiaxun
>>
>>>
>>> Thanks
>>> Jiaxun
>>>
>>> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>>> ---
>>> Jiaxun Yang (5):
>>>       hw/pci-host/bonito: Implement ICU
>>>       hw/pci-host/bonito: Implement PCIMAP register
>>>       hw/pci-host/bonito: Implement DMA address translation
>>>       hw/pci-host/bonito: Rework PCI config space accessor
>>>       hw/pci-host/bonito: Add comments about documentation
>>>
>>>  hw/pci-host/bonito.c     | 453 +++++++++++++++++++++++++++++------------------
>>>  hw/pci-host/trace-events |   3 -
>>>  2 files changed, 284 insertions(+), 172 deletions(-)
>>> ---
>>> base-commit: c5e2c4042e3c50b96cc5eaa9683325c5a96913b0
>>> change-id: 20250507-bonito-482759b2b52f
>>>
>>> Best regards,
>>> -- 
>>> Jiaxun Yang <jiaxun.yang@flygoat.com>
>>
>> -- 
>> - Jiaxun
>

Re: [PATCH 5/5] hw/pci-host/bonito: Add comments about documentation

[Bernhard Beschow]

Am 8. Mai 2025 14:46:10 UTC schrieb Jiaxun Yang <jiaxun.yang@flygoat.com>:
>Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>---
> hw/pci-host/bonito.c | 21 ++++++++++++++++-----
> 1 file changed, 16 insertions(+), 5 deletions(-)
>
>diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c
>index 49b4be26393a08eda4f99c8e2ef8a0c455c57bc0..918ee39661004d902d2deb25dd5e782855a11854 100644
>--- a/hw/pci-host/bonito.c
>+++ b/hw/pci-host/bonito.c
>@@ -1,5 +1,5 @@
> /*
>- * bonito north bridge support
>+ * Algorithmics Ltd BONITO north bridge emulation
>  *
>  * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
>  * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
>@@ -8,10 +8,21 @@
>  *
>  * Contributions after 2012-01-13 are licensed under the terms of the
>  * GNU GPL, version 2 or (at your option) any later version.
>- */
>-
>-/*
>- * fuloong 2e mini pc has a bonito north bridge.
>+ *
>+ * For 32-bit variant:
>+ * "BONITO - PCI/SDRAM System Controller for Vr43xx"
>+ * https://wiki.qemu.org/File:Bonito-spec.pdf
>+ *
>+ * "BONITO - Companion Chip for Vr43xx and Vr5xxx" (uPD65949S1-P00-F6)
>+ * https://repo.oss.cipunited.com/archives/docs/NEC/U15789EE1V0DS00.pdf

This one gives me a 404. This link works for me: https://www.renesas.com/ja/document/dst/upd65949s1-p00-f6-bonito-companion-chip-vr43xx-and-vr5xxx

>+ *
>+ * For 64-bit variant:
>+ * "BONITO64 - "north bridge" controller for 64-bit MIPS CPUs"
>+ * https://wiki.qemu.org/File:Bonito-spec.pdf

This is the link to the 32-bit variant. Correct link: https://wiki.qemu.org/File:Bonito64-spec.pdf

>+ *
>+ * For Godson (Loongson) 2E variant:
>+ * "Godson 2E North Bridge User Manual" (in Chinese)
>+ * https://github.com/loongson-community/docs/blob/master/2E/Godson_2E_NB_UM.pdf
>  */
> 
> #include "qemu/osdep.h"
>

Re: [PATCH 3/5] hw/pci-host/bonito: Implement DMA address translation

[Bernhard Beschow]

Am 8. Mai 2025 14:46:08 UTC schrieb Jiaxun Yang <jiaxun.yang@flygoat.com>:
>PCIBase (Host Bridge config space BARs) and PCIBaseCfg registers
>in Bonito controls PCI DMA address translation.
>
>For any incoming DMA requests, it will be matched against PCiBase{0, 1}
>together with PciBaseCfg.MASK{0,1}. If it hits any of both, higher bits
>of address will be replaced by PciBaseCfg.TRANSx.
>
>Emulating this behavior by PCI IOMMU DMA address space with dynamic
>remapping on register writes.
>
>Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>---
> hw/pci-host/bonito.c | 113 +++++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 113 insertions(+)
>
>diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c
>index f509f22df90ff7ed31ff5387a0acc239c22fd5f6..1c0d502a1e2dfa3c9803ca219cf505e08bf94a75 100644
>--- a/hw/pci-host/bonito.c
>+++ b/hw/pci-host/bonito.c
>@@ -144,6 +144,17 @@ FIELD(PCIMAP, LO2, 12, 6)
> FIELD(PCIMAP, 2, 18, 1)
> 
> #define BONITO_PCIMEMBASECFG    (0x14 >> 2)      /* 0x114 */
>+REG32(PCIMEMBASECFG, 0x114)
>+FIELD(PCIMEMBASECFG, MASK0, 0, 5)
>+FIELD(PCIMEMBASECFG, TRANS0, 5, 5)
>+FIELD(PCIMEMBASECFG, CACHED0, 10, 1)
>+FIELD(PCIMEMBASECFG, IO0, 11, 1)
>+FIELD(PCIMEMBASECFG, MASK1, 12, 5)
>+FIELD(PCIMEMBASECFG, TRANS1, 17, 5)
>+FIELD(PCIMEMBASECFG, CACHED1, 22, 1)
>+FIELD(PCIMEMBASECFG, IO1, 23, 1)
>+
>+
> #define BONITO_PCIMAP_CFG       (0x18 >> 2)      /* 0x118 */
> 
> /* 5. ICU & GPIO regs */
>@@ -258,9 +269,12 @@ struct BonitoState {
>     PCIHostState parent_obj;
>     qemu_irq *pic;
>     PCIBonitoState *pci_dev;
>+    MemoryRegion dma_mr;
>     MemoryRegion pci_mem;
>+    AddressSpace dma_as;
>     MemoryRegion *pcimem_lo_alias;
>     MemoryRegion *pcimem_hi_alias;
>+    MemoryRegion *dma_alias;

Should be `MemoryRegion dma_alias[2]` for simplicity and to avoid memory leaks.

> };
> 
> #define TYPE_PCI_BONITO "Bonito"
>@@ -314,6 +328,57 @@ static void bonito_update_pcimap(PCIBonitoState *s)
>                                    FIELD_EX32(pcimap, PCIMAP, 2) << 31);
> }
> 
>+static void pcibasecfg_decode(uint32_t mask, uint32_t trans, bool io,
>+                                     uint32_t *base, uint32_t *size)
>+{
>+    uint32_t val;
>+
>+    mask = (mask << 23 | 0xF0000000);
>+    val = ctz32(mask);
>+    *size = 1 << val;
>+    *base = (trans & ~(*size - 1)) | io << 28;
>+}
>+
>+static void bonito_update_pcibase(PCIBonitoState *s)
>+{
>+    uint32_t pcibasecfg = s->regs[BONITO_PCIMEMBASECFG];
>+    uint32_t size, base;
>+    uint32_t pcibase, wmask;
>+
>+    pcibasecfg_decode(FIELD_EX32(pcibasecfg, PCIMEMBASECFG, MASK0),
>+                      FIELD_EX32(pcibasecfg, PCIMEMBASECFG, TRANS0),
>+                      FIELD_EX32(pcibasecfg, PCIMEMBASECFG, IO0),
>+                      &base, &size);
>+
>+    wmask = ~(size - 1);
>+    /* Mask will also influence PCIBase register writable range */
>+    pci_set_long(s->dev.wmask + PCI_BASE_ADDRESS_0, wmask);
>+    /* Clear RO bits in PCIBase */
>+    pcibase = pci_get_long(s->dev.config + PCI_BASE_ADDRESS_0);
>+    pcibase &= wmask;
>+    pci_set_long(s->dev.config + PCI_BASE_ADDRESS_0, pcibase);
>+    /* Adjust DMA spaces */
>+    memory_region_set_size(&s->pcihost->dma_alias[0], size);
>+    memory_region_set_alias_offset(&s->pcihost->dma_alias[0], base);
>+    memory_region_set_address(&s->pcihost->dma_alias[0], pcibase);
>+
>+    /* Ditto for PCIMEMBASECFG1 */
>+    pcibasecfg_decode(FIELD_EX32(pcibasecfg, PCIMEMBASECFG, MASK1),
>+                      FIELD_EX32(pcibasecfg, PCIMEMBASECFG, TRANS1),
>+                      FIELD_EX32(pcibasecfg, PCIMEMBASECFG, IO1),
>+                      &base, &size);
>+
>+    wmask = ~(size - 1);
>+    pci_set_long(s->dev.wmask + PCI_BASE_ADDRESS_1, wmask);
>+    pcibase = pci_get_long(s->dev.config + PCI_BASE_ADDRESS_1);
>+    pcibase &= wmask;
>+    pci_set_long(s->dev.config + PCI_BASE_ADDRESS_1, pcibase);
>+
>+    memory_region_set_size(&s->pcihost->dma_alias[1], size);
>+    memory_region_set_alias_offset(&s->pcihost->dma_alias[1], base);
>+    memory_region_set_address(&s->pcihost->dma_alias[1], pcibase);
>+}
>+
> static void bonito_writel(void *opaque, hwaddr addr,
>                           uint64_t val, unsigned size)
> {
>@@ -624,12 +689,35 @@ static const MemoryRegionOps bonito_spciconf_ops = {
>     .endianness = DEVICE_NATIVE_ENDIAN,
> };
> 
>+static void bonito_pci_write_config(PCIDevice *dev, uint32_t address,
>+                                    uint32_t val, int len)
>+{
>+    pci_default_write_config(dev, address, val, len);
>+
>+    if (ranges_overlap(address, len, PCI_BASE_ADDRESS_0, 12)) {
>+        /* Bonito Host Bridge BARs are defined as DMA windows (pciBase) */
>+        bonito_update_pcibase(PCI_BONITO(dev));
>+    }
>+}
>+
> static int pci_bonito_map_irq(PCIDevice *pci_dev, int irq_num)
> {
>     /* Fuloong 2E PCI INTX are connected to Bonito GPIN[3:0] */
>     return ICU_PIN_GPINx(irq_num);
> }
> 
>+static AddressSpace *bonito_pcihost_set_iommu(PCIBus *bus, void *opaque,

s/set/get/ since it gets assigned to `get_address_space`.

>+                                              int devfn)
>+{
>+    BonitoState *bs = opaque;
>+
>+    return &bs->dma_as;
>+}
>+
>+static const PCIIOMMUOps bonito_iommu_ops = {
>+    .get_address_space = bonito_pcihost_set_iommu,
>+};
>+
> static void bonito_reset_hold(Object *obj, ResetType type)
> {
>     PCIBonitoState *s = PCI_BONITO(obj);
>@@ -653,6 +741,11 @@ static void bonito_reset_hold(Object *obj, ResetType type)
>     s->regs[BONITO_DQCFG] = 0x8;
>     s->regs[BONITO_MEMSIZE] = 0x10000000;
>     s->regs[BONITO_PCIMAP] = 0x6140;
>+    bonito_update_pcimap(s);
>+
>+    pci_set_long(s->dev.config + PCI_BASE_ADDRESS_0, 0x80000000);
>+    pci_set_long(s->dev.config + PCI_BASE_ADDRESS_1, 0x0);
>+    bonito_update_pcibase(s);
> }
> 
> static const VMStateDescription vmstate_bonito = {
>@@ -700,6 +793,7 @@ static void bonito_pci_realize(PCIDevice *dev, Error **errp)
>     PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
>     BonitoState *bs = s->pcihost;
>     MemoryRegion *pcimem_hi_alias = g_new(MemoryRegion, 1);
>+    MemoryRegion *dma_alias = g_new(MemoryRegion, 2);
> 
>     /*
>      * Bonito North Bridge, built on FPGA,
>@@ -764,6 +858,24 @@ static void bonito_pci_realize(PCIDevice *dev, Error **errp)
>                                 (hwaddr)BONITO_PCIHI_BASE + BONITO_PCIHI_SIZE,
>                                 2 * GiB);
> 
>+    /* 32bit DMA */
>+    memory_region_init(&bs->dma_mr, OBJECT(s), "dma.pciBase", 4 * GiB);
>+
>+    /* pciBase0, mapped to system RAM */
>+    memory_region_init_alias(&dma_alias[0], NULL, "pciBase0.mem.alias",
>+                             host_mem, 0x80000000, 256 * MiB);
>+    memory_region_add_subregion_overlap(&bs->dma_mr, 0, &dma_alias[0], 2);
>+
>+    /* pciBase1, mapped to system RAM */
>+    memory_region_init_alias(&dma_alias[1], NULL, "pciBase1.mem.alias",
>+                            host_mem, 0, 256 * MiB);
>+    memory_region_add_subregion_overlap(&bs->dma_mr, 0, &dma_alias[1], 1);
>+
>+    bs->dma_alias = dma_alias;
>+
>+    address_space_init(&bs->dma_as, &bs->dma_mr, "pciBase.dma");
>+    pci_setup_iommu(phb->bus, &bonito_iommu_ops, bs);
>+
>     /* set the default value of north bridge pci config */
>     pci_set_word(dev->config + PCI_COMMAND, 0x0000);
>     pci_set_word(dev->config + PCI_STATUS, 0x0000);
>@@ -806,6 +918,7 @@ static void bonito_pci_class_init(ObjectClass *klass, const void *data)
>     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
>     ResettableClass *rc = RESETTABLE_CLASS(klass);
> 
>+    k->config_write = bonito_pci_write_config;
>     rc->phases.hold = bonito_reset_hold;
>     k->realize = bonito_pci_realize;
>     k->vendor_id = 0xdf53;
>

With the above comments addressed:
Reviewed-by: Bernhard Beschow <shentey@gmail.com>

Re: [PATCH 1/5] hw/pci-host/bonito: Implement ICU

[Bernhard Beschow]

Am 8. Mai 2025 14:46:06 UTC schrieb Jiaxun Yang <jiaxun.yang@flygoat.com>:
>Implement interrupt controller on Bonito north bridge, as well
>as PCI INTx mapping as per Fuloong 2E's hardware connection.
>
>pci_bonito_set_irq is renamed to bonito_set_irq to reflect that
>it also sets other IRQs on chip.
>
>Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>---
> hw/pci-host/bonito.c | 96 ++++++++++++++++++++++++++++++----------------------
> 1 file changed, 56 insertions(+), 40 deletions(-)
>
>diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c
>index 7d6251a78d7e2e26803dd72968ca2ea7adcfe0e5..a599a1db4c068325b8c1aa8fb4a45f6b299b581b 100644
>--- a/hw/pci-host/bonito.c
>+++ b/hw/pci-host/bonito.c
>@@ -157,6 +157,22 @@ FIELD(BONGENCFG, PCIQUEUE,      12, 1)
> #define BONITO_INTEN            (0x38 >> 2)      /* 0x138 */
> #define BONITO_INTISR           (0x3c >> 2)      /* 0x13c */
> 
>+/* ICU Pins */
>+#define ICU_PIN_MBOXx(x)        (0 + (x))
>+#define ICU_PIN_DMARDY          4
>+#define ICU_PIN_DMAEMPTY        5
>+#define ICU_PIN_COPYRDY         6
>+#define ICU_PIN_COPYEMPTY       7
>+#define ICU_PIN_COPYERR         8
>+#define ICU_PIN_PCIIRQ          9
>+#define ICU_PIN_MASTERERR       10
>+#define ICU_PIN_SYSTEMERR       11
>+#define ICU_PIN_DRAMPERR        12
>+#define ICU_PIN_RETRYERR        13
>+#define ICU_PIN_INTTIMER        14
>+#define ICU_PIN_GPIOx(x)        (16 + (x))
>+#define ICU_PIN_GPINx(x)        (25 + (x))
>+
> /* PCI mail boxes */
> #define BONITO_PCIMAIL0_OFFSET    0x40
> #define BONITO_PCIMAIL1_OFFSET    0x44
>@@ -206,6 +222,7 @@ struct PCIBonitoState {
> 
>     BonitoState *pcihost;
>     uint32_t regs[BONITO_REGS];
>+    uint32_t icu_pin_state;
> 
>     struct bonldma {
>         uint32_t ldmactrl;
>@@ -242,6 +259,40 @@ struct BonitoState {
> #define TYPE_PCI_BONITO "Bonito"
> OBJECT_DECLARE_SIMPLE_TYPE(PCIBonitoState, PCI_BONITO)
> 
>+static void bonito_update_irq(PCIBonitoState *s)
>+{
>+    BonitoState *bs = s->pcihost;
>+    uint32_t inten = s->regs[BONITO_INTEN];
>+    uint32_t intisr = s->regs[BONITO_INTISR];
>+    uint32_t intpol = s->regs[BONITO_INTPOL];
>+    uint32_t intedge = s->regs[BONITO_INTEDGE];
>+    uint32_t pin_state = s->icu_pin_state;
>+    uint32_t level, edge;
>+
>+    pin_state = (pin_state & ~intpol) | (~pin_state & intpol);
>+
>+    level = pin_state & ~intedge;
>+    edge = (pin_state & ~intisr) & intedge;
>+
>+    intisr = (intisr & intedge) | level;
>+    intisr |= edge;
>+    intisr &= inten;
>+
>+    s->regs[BONITO_INTISR] = intisr;
>+
>+    qemu_set_irq(*bs->pic, !!intisr);
>+}
>+
>+static void bonito_set_irq(void *opaque, int irq, int level)
>+{
>+    BonitoState *bs = opaque;
>+    PCIBonitoState *s = bs->pci_dev;
>+
>+    s->icu_pin_state = deposit32(s->icu_pin_state, irq, 1, !!level);
>+
>+    bonito_update_irq(s);
>+}
>+
> static void bonito_writel(void *opaque, hwaddr addr,
>                           uint64_t val, unsigned size)
> {
>@@ -289,12 +340,12 @@ static void bonito_writel(void *opaque, hwaddr addr,
>         }
>         break;
>     case BONITO_INTENSET:
>-        s->regs[BONITO_INTENSET] = val;
>         s->regs[BONITO_INTEN] |= val;
>+        bonito_update_irq(s);
>         break;
>     case BONITO_INTENCLR:
>-        s->regs[BONITO_INTENCLR] = val;
>         s->regs[BONITO_INTEN] &= ~val;
>+        bonito_update_irq(s);
>         break;
>     case BONITO_INTEN:
>     case BONITO_INTISR:
>@@ -549,45 +600,10 @@ static const MemoryRegionOps bonito_spciconf_ops = {
>     .endianness = DEVICE_NATIVE_ENDIAN,
> };
> 
>-#define BONITO_IRQ_BASE 32
>-
>-static void pci_bonito_set_irq(void *opaque, int irq_num, int level)
>-{
>-    BonitoState *s = opaque;
>-    qemu_irq *pic = s->pic;
>-    PCIBonitoState *bonito_state = s->pci_dev;
>-    int internal_irq = irq_num - BONITO_IRQ_BASE;
>-
>-    if (bonito_state->regs[BONITO_INTEDGE] & (1 << internal_irq)) {
>-        qemu_irq_pulse(*pic);
>-    } else {   /* level triggered */
>-        if (bonito_state->regs[BONITO_INTPOL] & (1 << internal_irq)) {
>-            qemu_irq_raise(*pic);
>-        } else {
>-            qemu_irq_lower(*pic);
>-        }
>-    }
>-}
>-
>-/* map the original irq (0~3) to bonito irq (16~47, but 16~31 are unused) */
> static int pci_bonito_map_irq(PCIDevice *pci_dev, int irq_num)
> {
>-    int slot;
>-
>-    slot = PCI_SLOT(pci_dev->devfn);
>-
>-    switch (slot) {
>-    case 5:   /* FULOONG2E_VIA_SLOT, SouthBridge, IDE, USB, ACPI, AC97, MC97 */
>-        return irq_num % 4 + BONITO_IRQ_BASE;
>-    case 6:   /* FULOONG2E_ATI_SLOT, VGA */
>-        return 4 + BONITO_IRQ_BASE;
>-    case 7:   /* FULOONG2E_RTL_SLOT, RTL8139 */
>-        return 5 + BONITO_IRQ_BASE;
>-    case 8 ... 12: /* PCI slot 1 to 4 */
>-        return (slot - 8 + irq_num) + 6 + BONITO_IRQ_BASE;
>-    default:  /* Unknown device, don't do any translation */
>-        return irq_num;
>-    }
>+    /* Fuloong 2E PCI INTX are connected to Bonito GPIN[3:0] */

Given this comment, doesn't this code belong into fuloong2e.c? See https://lore.kernel.org/qemu-devel/20230105154440.259361-1-shentey@gmail.com .

>+    return ICU_PIN_GPINx(irq_num);

It would then make sense to export this define. I can rebase my series, or how about incorporating it here? Either way:

Reviewed-by: Bernhard Beschow <shentey@gmail.com>

> }
> 
> static void bonito_reset_hold(Object *obj, ResetType type)
>@@ -633,7 +649,7 @@ static void bonito_host_realize(DeviceState *dev, Error **errp)
> 
>     memory_region_init(&bs->pci_mem, OBJECT(dev), "pci.mem", BONITO_PCIHI_SIZE);
>     phb->bus = pci_register_root_bus(dev, "pci",
>-                                     pci_bonito_set_irq, pci_bonito_map_irq,
>+                                     bonito_set_irq, pci_bonito_map_irq,
>                                      dev, &bs->pci_mem, get_system_io(),
>                                      PCI_DEVFN(5, 0), 32, TYPE_PCI_BUS);
> 
>

Re: [PATCH 2/5] hw/pci-host/bonito: Implement PCIMAP register

[Bernhard Beschow]

Am 8. Mai 2025 14:46:07 UTC schrieb Jiaxun Yang <jiaxun.yang@flygoat.com>:
>PCIMAP controls how PCILO and PCIHi regions map into
>PCI memory space.
>
>Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>---
> hw/pci-host/bonito.c | 37 ++++++++++++++++++++++++++++++++-----
> 1 file changed, 32 insertions(+), 5 deletions(-)
>
>diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c
>index a599a1db4c068325b8c1aa8fb4a45f6b299b581b..f509f22df90ff7ed31ff5387a0acc239c22fd5f6 100644
>--- a/hw/pci-host/bonito.c
>+++ b/hw/pci-host/bonito.c
>@@ -137,6 +137,12 @@ FIELD(BONGENCFG, PCIQUEUE,      12, 1)
> 
> /* 4. PCI address map control */
> #define BONITO_PCIMAP           (0x10 >> 2)      /* 0x110 */
>+REG32(PCIMAP,        0x110)
>+FIELD(PCIMAP, LO0, 0, 6)
>+FIELD(PCIMAP, LO1, 6, 6)
>+FIELD(PCIMAP, LO2, 12, 6)
>+FIELD(PCIMAP, 2, 18, 1)
>+
> #define BONITO_PCIMEMBASECFG    (0x14 >> 2)      /* 0x114 */
> #define BONITO_PCIMAP_CFG       (0x18 >> 2)      /* 0x118 */
> 
>@@ -245,7 +251,6 @@ struct PCIBonitoState {
>     MemoryRegion iomem_cop;
>     MemoryRegion bonito_pciio;
>     MemoryRegion bonito_localio;
>-
> };
> typedef struct PCIBonitoState PCIBonitoState;
> 
>@@ -254,6 +259,8 @@ struct BonitoState {
>     qemu_irq *pic;
>     PCIBonitoState *pci_dev;
>     MemoryRegion pci_mem;
>+    MemoryRegion *pcimem_lo_alias;
>+    MemoryRegion *pcimem_hi_alias;

These should be (arrays of) values rather than pointers for simplicity and to avoid memory leaks.

With this fixed:
Reviewed-by: Bernhard Beschow <shentey@gmail.com>

> };
> 
> #define TYPE_PCI_BONITO "Bonito"
>@@ -293,6 +300,20 @@ static void bonito_set_irq(void *opaque, int irq, int level)
>     bonito_update_irq(s);
> }
> 
>+static void bonito_update_pcimap(PCIBonitoState *s)
>+{
>+    uint32_t pcimap = s->regs[BONITO_PCIMAP];
>+
>+    memory_region_set_alias_offset(&s->pcihost->pcimem_lo_alias[0],
>+                                   FIELD_EX32(pcimap, PCIMAP, LO0) << 26);
>+    memory_region_set_alias_offset(&s->pcihost->pcimem_lo_alias[1],
>+                                   FIELD_EX32(pcimap, PCIMAP, LO1) << 26);
>+    memory_region_set_alias_offset(&s->pcihost->pcimem_lo_alias[2],
>+                                   FIELD_EX32(pcimap, PCIMAP, LO2) << 26);
>+    memory_region_set_alias_offset(s->pcihost->pcimem_hi_alias,
>+                                   FIELD_EX32(pcimap, PCIMAP, 2) << 31);
>+}
>+
> static void bonito_writel(void *opaque, hwaddr addr,
>                           uint64_t val, unsigned size)
> {
>@@ -308,7 +329,6 @@ static void bonito_writel(void *opaque, hwaddr addr,
>     case BONITO_BONPONCFG:
>     case BONITO_IODEVCFG:
>     case BONITO_SDCFG:
>-    case BONITO_PCIMAP:
>     case BONITO_PCIMEMBASECFG:
>     case BONITO_PCIMAP_CFG:
>     case BONITO_GPIODATA:
>@@ -330,6 +350,10 @@ static void bonito_writel(void *opaque, hwaddr addr,
>     case BONITO_MEMSIZE:
>         s->regs[saddr] = val;
>         break;
>+    case BONITO_PCIMAP:
>+        s->regs[BONITO_PCIMAP] = val;
>+        bonito_update_pcimap(s);
>+        break;
>     case BONITO_BONGENCFG:
>         if (!(s->regs[saddr] & 0x04) && (val & 0x04)) {
>             reset = 1; /* bit 2 jump from 0 to 1 cause reset */
>@@ -664,6 +688,8 @@ static void bonito_host_realize(DeviceState *dev, Error **errp)
>         g_free(name);
>     }
> 
>+    bs->pcimem_lo_alias = pcimem_lo_alias;
>+
>     create_unimplemented_device("pci.io", BONITO_PCIIO_BASE, 1 * MiB);
> }
> 
>@@ -673,7 +699,7 @@ static void bonito_pci_realize(PCIDevice *dev, Error **errp)
>     MemoryRegion *host_mem = get_system_memory();
>     PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
>     BonitoState *bs = s->pcihost;
>-    MemoryRegion *pcimem_alias = g_new(MemoryRegion, 1);
>+    MemoryRegion *pcimem_hi_alias = g_new(MemoryRegion, 1);
> 
>     /*
>      * Bonito North Bridge, built on FPGA,
>@@ -730,9 +756,10 @@ static void bonito_pci_realize(PCIDevice *dev, Error **errp)
>     create_unimplemented_device("IOCS[3]", BONITO_DEV_BASE + 3 * 256 * KiB,
>                                 256 * KiB);
> 
>-    memory_region_init_alias(pcimem_alias, NULL, "pci.mem.alias",
>+    memory_region_init_alias(pcimem_hi_alias, NULL, "pci.memhi.alias",
>                              &bs->pci_mem, 0, BONITO_PCIHI_SIZE);
>-    memory_region_add_subregion(host_mem, BONITO_PCIHI_BASE, pcimem_alias);
>+    memory_region_add_subregion(host_mem, BONITO_PCIHI_BASE, pcimem_hi_alias);
>+    bs->pcimem_hi_alias = pcimem_hi_alias;
>     create_unimplemented_device("PCI_2",
>                                 (hwaddr)BONITO_PCIHI_BASE + BONITO_PCIHI_SIZE,
>                                 2 * GiB);
>

Re: [PATCH 4/5] hw/pci-host/bonito: Rework PCI config space accessor

[Bernhard Beschow]

Am 8. Mai 2025 14:46:09 UTC schrieb Jiaxun Yang <jiaxun.yang@flygoat.com>:
>The original PCI config space accessor failed to issue master abort
>interrupt as necessary, it also didn't handle type 1 access and
>using south bridge concept which doesn't exist in Bonito.
>
>Rework the whole mechanism accorading to the manual, also remove
>inaccurate comments.
>
>Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>---
> hw/pci-host/bonito.c     | 202 ++++++++++++++++++-----------------------------
> hw/pci-host/trace-events |   3 -
> 2 files changed, 75 insertions(+), 130 deletions(-)
>
>diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c
>index 1c0d502a1e2dfa3c9803ca219cf505e08bf94a75..49b4be26393a08eda4f99c8e2ef8a0c455c57bc0 100644
>--- a/hw/pci-host/bonito.c
>+++ b/hw/pci-host/bonito.c
>@@ -14,30 +14,6 @@
>  * fuloong 2e mini pc has a bonito north bridge.
>  */
> 
>-/*
>- * what is the meaning of devfn in qemu and IDSEL in bonito northbridge?
>- *
>- * devfn   pci_slot<<3  + funno
>- * one pci bus can have 32 devices and each device can have 8 functions.
>- *
>- * In bonito north bridge, pci slot = IDSEL bit - 12.
>- * For example, PCI_IDSEL_VIA686B = 17,
>- * pci slot = 17-12=5
>- *
>- * so
>- * VT686B_FUN0's devfn = (5<<3)+0
>- * VT686B_FUN1's devfn = (5<<3)+1
>- *
>- * qemu also uses pci address for north bridge to access pci config register.
>- * bus_no   [23:16]
>- * dev_no   [15:11]
>- * fun_no   [10:8]
>- * reg_no   [7:2]
>- *
>- * so function bonito_sbridge_pciaddr for the translation from
>- * north bridge address to pci address.
>- */
>-
> #include "qemu/osdep.h"
> #include "qemu/units.h"
> #include "qapi/error.h"
>@@ -106,11 +82,6 @@
> #define BONITO_INTERNAL_REG_BASE  (BONITO_REGBASE + BONITO_REG_BASE)
> #define BONITO_INTERNAL_REG_SIZE  (0x70)
> 
>-#define BONITO_SPCICONFIG_BASE  (BONITO_PCICFG_BASE)
>-#define BONITO_SPCICONFIG_SIZE  (BONITO_PCICFG_SIZE)
>-
>-
>-
> /* 1. Bonito h/w Configuration */
> /* Power on register */
> 
>@@ -156,6 +127,9 @@ FIELD(PCIMEMBASECFG, IO1, 23, 1)
> 
> 
> #define BONITO_PCIMAP_CFG       (0x18 >> 2)      /* 0x118 */
>+REG32(PCIMAP_CFG,    0x118)
>+FIELD(PCIMAP_CFG, AD16UP, 0, 16)
>+FIELD(PCIMAP_CFG, TYPE1, 16, 1)
> 
> /* 5. ICU & GPIO regs */
> /* GPIO Regs - r/w */
>@@ -214,23 +188,14 @@ FIELD(PCIMEMBASECFG, IO1, 23, 1)
> 
> #define BONITO_REGS             (0x70 >> 2)
> 
>-/* PCI config for south bridge. type 0 */
>-#define BONITO_PCICONF_IDSEL_MASK      0xfffff800     /* [31:11] */
>-#define BONITO_PCICONF_IDSEL_OFFSET    11
>-#define BONITO_PCICONF_FUN_MASK        0x700    /* [10:8] */
>-#define BONITO_PCICONF_FUN_OFFSET      8
>-#define BONITO_PCICONF_REG_MASK_DS     (~3)         /* Per datasheet */
>-#define BONITO_PCICONF_REG_MASK_HW     0xff         /* As seen running PMON */
>-#define BONITO_PCICONF_REG_OFFSET      0
>-
>+/* PCI Access Cycle Fields */
>+FIELD(TYPE0_CYCLE, FUNC, 8, 3)
>+FIELD(TYPE0_CYCLE, IDSEL, 11, 21)
> 
>-/* idsel BIT = pci slot number +12 */
>-#define PCI_SLOT_BASE              12
>-#define PCI_IDSEL_VIA686B_BIT      (17)
>-#define PCI_IDSEL_VIA686B          (1 << PCI_IDSEL_VIA686B_BIT)
>-
>-#define PCI_ADDR(busno , devno , funno , regno)  \
>-    ((PCI_BUILD_BDF(busno, PCI_DEVFN(devno , funno)) << 8) + (regno))
>+FIELD(TYPE1_CYCLE, FUNC, 8, 3)
>+FIELD(TYPE1_CYCLE, DEV, 11, 5)
>+FIELD(TYPE1_CYCLE, BUS, 16, 8)
>+FIELD(TYPE1_CYCLE, IDSEL, 24, 8)
> 
> typedef struct BonitoState BonitoState;
> 
>@@ -580,108 +545,91 @@ static const MemoryRegionOps bonito_cop_ops = {
>     },
> };
> 
>-static uint32_t bonito_sbridge_pciaddr(void *opaque, hwaddr addr)
>+static PCIDevice *bonito_pcihost_cfg_decode(PCIBonitoState *s, hwaddr addr)
> {
>-    PCIBonitoState *s = opaque;
>     PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
>-    uint32_t cfgaddr;
>-    uint32_t idsel;
>-    uint32_t devno;
>-    uint32_t funno;
>-    uint32_t regno;
>-    uint32_t pciaddr;
>-
>-    /* support type0 pci config */
>-    if ((s->regs[BONITO_PCIMAP_CFG] & 0x10000) != 0x0) {
>-        return 0xffffffff;
>+    uint32_t pcimap_cfg = s->regs[BONITO_PCIMAP_CFG];
>+    uint32_t cycle, dev, func, bus;
>+
>+    cycle = addr | FIELD_EX32(pcimap_cfg, PCIMAP_CFG, AD16UP) << 16;
>+
>+    if (FIELD_EX32(pcimap_cfg, PCIMAP_CFG, TYPE1)) {
>+        dev = FIELD_EX32(cycle, TYPE1_CYCLE, DEV);
>+        func = FIELD_EX32(cycle, TYPE1_CYCLE, FUNC);
>+        bus = FIELD_EX32(cycle, TYPE1_CYCLE, BUS);
>+    } else {
>+        uint32_t idsel = FIELD_EX32(cycle, TYPE0_CYCLE, IDSEL);
>+        if (idsel == 0) {
>+            return NULL;
>+        }
>+        dev = ctz32(idsel);
>+        func = FIELD_EX32(cycle, TYPE0_CYCLE, FUNC);
>+        bus = 0;
>     }
> 
>-    cfgaddr = addr & 0xffff;
>-    cfgaddr |= (s->regs[BONITO_PCIMAP_CFG] & 0xffff) << 16;
>+    return pci_find_device(phb->bus, bus, PCI_DEVFN(dev, func));
>+}
> 
>-    idsel = (cfgaddr & BONITO_PCICONF_IDSEL_MASK) >>
>-             BONITO_PCICONF_IDSEL_OFFSET;
>-    devno = ctz32(idsel);
>-    funno = (cfgaddr & BONITO_PCICONF_FUN_MASK) >> BONITO_PCICONF_FUN_OFFSET;
>-    regno = (cfgaddr & BONITO_PCICONF_REG_MASK_HW) >> BONITO_PCICONF_REG_OFFSET;
>+static void bonito_pcihost_signal_mabort(PCIBonitoState *s)
>+{
>+    PCIDevice *d = &s->dev;
>+    uint16_t status = pci_get_word(d->config + PCI_STATUS);
> 
>-    if (idsel == 0) {
>-        error_report("error in bonito pci config address 0x" HWADDR_FMT_plx
>-                     ",pcimap_cfg=0x%x", addr, s->regs[BONITO_PCIMAP_CFG]);
>-        exit(1);
>-    }
>-    pciaddr = PCI_ADDR(pci_bus_num(phb->bus), devno, funno, regno);
>-    DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d\n",
>-        cfgaddr, pciaddr, pci_bus_num(phb->bus), devno, funno, regno);
>+    status |= PCI_STATUS_REC_MASTER_ABORT;
>+    pci_set_word(d->config + PCI_STATUS, status);
> 
>-    return pciaddr;
>+    /* Generate a pulse, it's a edge triggered IRQ */
>+    bonito_set_irq(s->pcihost, ICU_PIN_MASTERERR, 1);
>+    bonito_set_irq(s->pcihost, ICU_PIN_MASTERERR, 0);
> }
> 
>-static void bonito_spciconf_write(void *opaque, hwaddr addr, uint64_t val,
>-                                  unsigned size)
>+static MemTxResult bonito_pcihost_cfg_read(void *opaque, hwaddr addr,
>+                                           uint64_t *data, unsigned len,
>+                                           MemTxAttrs attrs)
> {
>     PCIBonitoState *s = opaque;
>-    PCIDevice *d = PCI_DEVICE(s);
>-    PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
>-    uint32_t pciaddr;
>-    uint16_t status;
>-
>-    DPRINTF("bonito_spciconf_write "HWADDR_FMT_plx" size %d val %lx\n",
>-            addr, size, val);
>-
>-    pciaddr = bonito_sbridge_pciaddr(s, addr);
>-
>-    if (pciaddr == 0xffffffff) {
>-        return;
>-    }
>-    if (addr & ~BONITO_PCICONF_REG_MASK_DS) {
>-        trace_bonito_spciconf_small_access(addr, size);
>+    PCIDevice *dev;
>+
>+    dev = bonito_pcihost_cfg_decode(s, addr);
>+    if (!dev) {
>+        bonito_pcihost_signal_mabort(s);
>+        /*
>+         * Vanilla bonito will actually triiger a bus error on master abort,
>+         * Godson variant won't. We need to return all 1s.
>+         */
>+        *data = UINT64_MAX;
>+        return MEMTX_OK;
>     }
> 
>-    /* set the pci address in s->config_reg */
>-    phb->config_reg = (pciaddr) | (1u << 31);
>-    pci_data_write(phb->bus, phb->config_reg, val, size);
>+    addr &= PCI_CONFIG_SPACE_SIZE - 1;
>+    *data = pci_host_config_read_common(dev, addr, pci_config_size(dev), len);
> 
>-    /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
>-    status = pci_get_word(d->config + PCI_STATUS);
>-    status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
>-    pci_set_word(d->config + PCI_STATUS, status);
>+    return MEMTX_OK;
> }
> 
>-static uint64_t bonito_spciconf_read(void *opaque, hwaddr addr, unsigned size)
>+static MemTxResult bonito_pcihost_cfg_write(void *opaque, hwaddr addr,
>+                                            uint64_t data, unsigned len,
>+                                            MemTxAttrs attrs)
> {
>     PCIBonitoState *s = opaque;
>-    PCIDevice *d = PCI_DEVICE(s);
>-    PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
>-    uint32_t pciaddr;
>-    uint16_t status;
>-
>-    DPRINTF("bonito_spciconf_read "HWADDR_FMT_plx" size %d\n", addr, size);
>+    PCIDevice *dev;
> 
>-    pciaddr = bonito_sbridge_pciaddr(s, addr);
>-
>-    if (pciaddr == 0xffffffff) {
>-        return MAKE_64BIT_MASK(0, size * 8);
>-    }
>-    if (addr & ~BONITO_PCICONF_REG_MASK_DS) {
>-        trace_bonito_spciconf_small_access(addr, size);
>+    dev = bonito_pcihost_cfg_decode(s, addr);
>+    if (!dev) {
>+        bonito_pcihost_signal_mabort(s);
>+        return MEMTX_OK;
>     }
> 
>-    /* set the pci address in s->config_reg */
>-    phb->config_reg = (pciaddr) | (1u << 31);
>-
>-    /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
>-    status = pci_get_word(d->config + PCI_STATUS);
>-    status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
>-    pci_set_word(d->config + PCI_STATUS, status);
>+    addr &= PCI_CONFIG_SPACE_SIZE - 1;
>+    pci_host_config_write_common(dev, addr, pci_config_size(dev), data, len);
> 
>-    return pci_data_read(phb->bus, phb->config_reg, size);
>+    return MEMTX_OK;
> }
> 
>-/* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */
>-static const MemoryRegionOps bonito_spciconf_ops = {
>-    .read = bonito_spciconf_read,
>-    .write = bonito_spciconf_write,
>+/* PCI Configure Space access region. 0x1fe8 0000 - 0x1fef ffff */

s/Configure Space/configuration space/

Reviewed-by: Bernhard Beschow <shentey@gmail.com>

>+static const MemoryRegionOps bonito_pcihost_cfg_ops = {
>+    .read_with_attrs = bonito_pcihost_cfg_read,
>+    .write_with_attrs = bonito_pcihost_cfg_write,
>     .valid.min_access_size = 1,
>     .valid.max_access_size = 4,
>     .impl.min_access_size = 1,
>@@ -812,10 +760,10 @@ static void bonito_pci_realize(PCIDevice *dev, Error **errp)
>     memory_region_add_subregion(host_mem, BONITO_PCICONFIG_BASE,
>                                 &phb->conf_mem);
> 
>-    /* set the south bridge pci configure  mapping */
>-    memory_region_init_io(&phb->data_mem, OBJECT(s), &bonito_spciconf_ops, s,
>-                          "south-bridge-pci-config", BONITO_SPCICONFIG_SIZE);
>-    memory_region_add_subregion(host_mem, BONITO_SPCICONFIG_BASE,
>+    /* set the pci config space accessor mapping */
>+    memory_region_init_io(&phb->data_mem, OBJECT(s), &bonito_pcihost_cfg_ops, s,
>+                          "pci-host-config-access", BONITO_PCICFG_SIZE);
>+    memory_region_add_subregion(host_mem, BONITO_PCICFG_BASE,
>                                 &phb->data_mem);
> 
>     create_unimplemented_device("bonito", BONITO_REG_BASE, BONITO_REG_SIZE);
>diff --git a/hw/pci-host/trace-events b/hw/pci-host/trace-events
>index 0a816b9aa129bb0c37d207e2612e09ac4762d51a..bd9bdeadfd3678e303a412688d689cc01d06f709 100644
>--- a/hw/pci-host/trace-events
>+++ b/hw/pci-host/trace-events
>@@ -1,8 +1,5 @@
> # See docs/devel/tracing.rst for syntax documentation.
> 
>-# bonito.c
>-bonito_spciconf_small_access(uint64_t addr, unsigned size) "PCI config address is smaller then 32-bit, addr: 0x%"PRIx64", size: %u"
>-
> # grackle.c
> grackle_set_irq(int irq_num, int level) "set_irq num %d level %d"
> 
>

Re: [PATCH 5/5] hw/pci-host/bonito: Add comments about documentation

[Bernhard Beschow]

Am 9. September 2025 07:14:00 UTC schrieb Bernhard Beschow <shentey@gmail.com>:
>
>
>Am 8. Mai 2025 14:46:10 UTC schrieb Jiaxun Yang <jiaxun.yang@flygoat.com>:
>>Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>>---
>> hw/pci-host/bonito.c | 21 ++++++++++++++++-----
>> 1 file changed, 16 insertions(+), 5 deletions(-)
>>
>>diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c
>>index 49b4be26393a08eda4f99c8e2ef8a0c455c57bc0..918ee39661004d902d2deb25dd5e782855a11854 100644
>>--- a/hw/pci-host/bonito.c
>>+++ b/hw/pci-host/bonito.c
>>@@ -1,5 +1,5 @@
>> /*
>>- * bonito north bridge support
>>+ * Algorithmics Ltd BONITO north bridge emulation
>>  *
>>  * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
>>  * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
>>@@ -8,10 +8,21 @@
>>  *
>>  * Contributions after 2012-01-13 are licensed under the terms of the
>>  * GNU GPL, version 2 or (at your option) any later version.
>>- */
>>-
>>-/*
>>- * fuloong 2e mini pc has a bonito north bridge.
>>+ *
>>+ * For 32-bit variant:
>>+ * "BONITO - PCI/SDRAM System Controller for Vr43xx"
>>+ * https://wiki.qemu.org/File:Bonito-spec.pdf
>>+ *
>>+ * "BONITO - Companion Chip for Vr43xx and Vr5xxx" (uPD65949S1-P00-F6)
>>+ * https://repo.oss.cipunited.com/archives/docs/NEC/U15789EE1V0DS00.pdf
>
>This one gives me a 404. This link works for me: https://www.renesas.com/ja/document/dst/upd65949s1-p00-f6-bonito-companion-chip-vr43xx-and-vr5xxx
>
>>+ *
>>+ * For 64-bit variant:
>>+ * "BONITO64 - "north bridge" controller for 64-bit MIPS CPUs"
>>+ * https://wiki.qemu.org/File:Bonito-spec.pdf
>
>This is the link to the 32-bit variant. Correct link: https://wiki.qemu.org/File:Bonito64-spec.pdf

With the two links fixed:
Reviewed-by: Bernhard Beschow <shentey@gmail.com>

>
>>+ *
>>+ * For Godson (Loongson) 2E variant:
>>+ * "Godson 2E North Bridge User Manual" (in Chinese)
>>+ * https://github.com/loongson-community/docs/blob/master/2E/Godson_2E_NB_UM.pdf
>>  */
>> 
>> #include "qemu/osdep.h"
>>

Re: [PATCH 0/5] hw/pci-host/bonito: Improve various emulation functions

[Bernhard Beschow]

Am 8. Mai 2025 14:46:05 UTC schrieb Jiaxun Yang <jiaxun.yang@flygoat.com>:
>Hi all,
>
>This series addressed a couple of missing Bonito functionalities
>I found when I was trying to test NetBSD against QEMU.
Nice work! With this series in combination with <https://lore.kernel.org/qemu-devel/20250914185526.3622-1-shentey@gmail.com/> I'm also able to start PMON2000!

Could you share some details on how to run NetBSD on this machine, please?

>
>Please review.

[X] Done

Best regards,
Bernhard

>
>Thanks
>Jiaxun
>
>Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>---
>Jiaxun Yang (5):
>      hw/pci-host/bonito: Implement ICU
>      hw/pci-host/bonito: Implement PCIMAP register
>      hw/pci-host/bonito: Implement DMA address translation
>      hw/pci-host/bonito: Rework PCI config space accessor
>      hw/pci-host/bonito: Add comments about documentation
>
> hw/pci-host/bonito.c     | 453 +++++++++++++++++++++++++++++------------------
> hw/pci-host/trace-events |   3 -
> 2 files changed, 284 insertions(+), 172 deletions(-)
>---
>base-commit: c5e2c4042e3c50b96cc5eaa9683325c5a96913b0
>change-id: 20250507-bonito-482759b2b52f
>
>Best regards,