Re: [PATCH v9 1/2] Set KVM initial privilege mode and mp_state

["Radim Krčmář" <rkrcmar@ventanamicro.com>]

2025-09-15T15:08:07+08:00, Xie Bo <xb@ultrarisc.com>:
> For KVM mode, the privilege mode should not include M-mode, and the
> initial value should be set to S-mode. Additionally, a following patch
> adds the implementation of putting the vCPU privilege mode to KVM.
> When the vCPU runs for the first time, QEMU will first put the privilege
> state to KVM. If the initial value is set to M-mode, KVM will encounter
> an error.
>
> In addition, this patch introduces the 'mp_state' field to RISC-V
> vCPUs, following the convention used by KVM on x86. The 'mp_state'
> reflects the multiprocessor state of a vCPU, and is used to control
> whether the vCPU is runnable by KVM. Randomly select one CPU as the
> boot CPU. Since each CPU executes the riscv_cpu_reset_hold() function
> and CPU0 executes first, only CPU0 randomly selects the boot CPU.

This could really be two patches, as changing the boot 

> Signed-off-by: Xie Bo <xb@ultrarisc.com>
> ---
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> @@ -685,18 +686,32 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
> +    static int boot_cpu_index;
       ^^^^^^
!

> +    if (kvm_enabled()) {
> +        env->priv = PRV_S;
> +    } else {
> +        env->priv = PRV_M;
> +    }

(I think changing the priv belongs to a separate patch.)

> +    if (cs->cpu_index == 0) {
> +        boot_cpu_index = g_random_int_range(0, ms->smp.cpus);
> +    }

This adds an assumption that vcpu_index == 0 is executed first.
Is that always going to be true?

If we reset the VCPUs in a different order (or in parallel), we might
also online zero or two VCPUs.

Performing the selection just once, in the reset initiator, would allow
us to avoid the dreaded static variable by putting it in machine arch
state.

> +    if (cs->cpu_index == boot_cpu_index) {
> +        env->mp_state = KVM_MP_STATE_RUNNABLE;
> +    } else {
> +        env->mp_state = KVM_MP_STATE_STOPPED;
> +    }

Thanks.