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Tue, 4 Nov 2025 14:13:22 -0500 (EST) Received: from localhost (chomposaur [local]) by chomposaur (OpenSMTPD) with ESMTPA id f43d87ba; Tue, 4 Nov 2025 19:13:20 +0000 (UTC) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Tue, 04 Nov 2025 14:13:20 -0500 Message-Id: Cc: , "Gerd Hoffmann" , , Subject: Re: [PATCH] ati-vga: Separate default control bit for source From: "Chad Jablonski" To: "BALATON Zoltan" , "Chad Jablonski" X-Mailer: aerc 0.21.0 References: <20251007195435.8ACAC56F2A3@zero.eik.bme.hu> <9830b63d-4a83-0c58-3ce4-c2a19fd47efa@eik.bme.hu> In-Reply-To: <9830b63d-4a83-0c58-3ce4-c2a19fd47efa@eik.bme.hu> Received-SPF: pass client-ip=202.12.124.157; envelope-from=chad@jablonski.xyz; helo=fhigh-b6-smtp.messagingengine.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FROM_SUSPICIOUS_NTLD=0.499, PDS_OTHER_BAD_TLD=0.001, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org > > Matching hardware is more important than matching style, after all this i= s > supposed to emulate hardware and we already found places where the docs > were wrong. So if you can test and match what hardware does that would be > best. > I just tested this using the same environment I tested the clipping fields with and it looks like offset and pitch also latch to default values: Test SRC pitch and offset =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D ** Initializing DEFAULT_OFFSET to 0x0 ** ** Initializing DEFAULT_PITCH to 0x0 ** ** Initializing SRC_OFFSET to 0x0 ** ** Initializing SRC_PITCH to 0x0 ** Initial State ------------------------------------ DP_GUI_MASTER_CNTL: 0x30f0e00d DEFAULT_OFFSET: 0x00000000 DEFAULT_PITCH: 0x00000000 SRC_OFFSET: 0x00000000 SRC_PITCH: 0x00000000 ** Setting DEFAULT_OFFSET to 0x000000aa ** ** Setting DEFAULT_PITCH to 0x000000bb ** ** Setting SRC_OFFSET to 0x11 ** ** Setting SRC_PITCH to 0x22 ** State After Setting ------------------------------------ DP_GUI_MASTER_CNTL: 0x30f0e00d DEFAULT_OFFSET: 0x000000a0 <=3D=3D=3D=3D=3D=3D=3D 4:0 are hardwir= ed to 0 DEFAULT_PITCH: 0x000000bb just like the docs say SRC_OFFSET: 0x00000010 <=3D=3D=3D=3D=3D=3D=3D 4:0 are hardwir= ed to 0 SRC_PITCH: 0x00000022 just like the docs say ** Setting GMC_SRC_PITCH_OFFSET_CNTL to default ** State After Setting Default ------------------------------------ DP_GUI_MASTER_CNTL: 0x30f0e00c DEFAULT_OFFSET: 0x000000a0 DEFAULT_PITCH: 0x000000bb SRC_OFFSET: 0x000000a0 <=3D=3D=3D=3D=3D=3D=3D Set to default SRC_PITCH: 0x000000bb <=3D=3D=3D=3D=3D=3D=3D Set to default ** Setting GMC_SRC_PITCH_OFFSET_CNTL to leave alone ** State After Setting Leave Alone ------------------------------------ DP_GUI_MASTER_CNTL: 0x30f0e00d DEFAULT_OFFSET: 0x000000a0 DEFAULT_PITCH: 0x000000bb SRC_OFFSET: 0x000000a0 <=3D=3D=3D=3D=3D=3D=3D STILL default SRC_PITCH: 0x000000bb <=3D=3D=3D=3D=3D=3D=3D STILL default Test DST pitch and offset =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D ** Initializing DEFAULT_OFFSET to 0x0 ** ** Initializing DEFAULT_PITCH to 0x0 ** ** Initializing DST_OFFSET to 0x0 ** ** Initializing DST_PITCH to 0x0 ** Initial State ------------------------------------ DP_GUI_MASTER_CNTL: 0x30f0e00d DEFAULT_OFFSET: 0x00000000 DEFAULT_PITCH: 0x00000000 DST_OFFSET: 0x00000000 DST_PITCH: 0x00000000 ** Setting DEFAULT_OFFSET to 0x000000aa ** ** Setting DEFAULT_PITCH to 0x000000bb ** ** Setting DST_OFFSET to 0x11 ** ** Setting DST_PITCH to 0x22 ** State After Setting ------------------------------------ DP_GUI_MASTER_CNTL: 0x30f0e00d DEFAULT_OFFSET: 0x000000a0 <=3D=3D=3D=3D=3D=3D=3D 4:0 are hardwir= ed to 0 DEFAULT_PITCH: 0x000000bb just like the docs say DST_OFFSET: 0x00000010 <=3D=3D=3D=3D=3D=3D=3D 4:0 are hardwir= ed to 0 DST_PITCH: 0x00000022 just like the docs say ** Setting GMC_DST_PITCH_OFFSET_CNTL to default ** State After Setting Default ------------------------------------ DP_GUI_MASTER_CNTL: 0x30f0e00c DEFAULT_OFFSET: 0x000000a0 DEFAULT_PITCH: 0x000000bb DST_OFFSET: 0x000000a0 <=3D=3D=3D=3D=3D=3D=3D Set to default DST_PITCH: 0x000000bb <=3D=3D=3D=3D=3D=3D=3D Set to default ** Setting GMC_DST_PITCH_OFFSET_CNTL to leave alone ** State After Setting Leave Alone ------------------------------------ DP_GUI_MASTER_CNTL: 0x30f0e00d DEFAULT_OFFSET: 0x000000a0 DEFAULT_PITCH: 0x000000bb DST_OFFSET: 0x000000a0 <=3D=3D=3D=3D=3D=3D=3D STILL default DST_PITCH: 0x000000bb <=3D=3D=3D=3D=3D=3D=3D STILL default