Re: [PATCH 3/7] hw/riscv: implement CBQRI capacity controller

["Radim Krčmář" <rkrcmar@ventanamicro.com>]

2025-11-21T11:50:50-08:00, Drew Fustini <fustini@kernel.org>:
> On Thu, Nov 20, 2025 at 08:25:44PM +0100, Radim Krčmář wrote:
>> 2025-11-19T16:42:19-08:00, Drew Fustini <fustini@kernel.org>:
>> > +static void riscv_cbqri_cc_realize(DeviceState *dev, Error **errp)
>> > +{
>> > +    RiscvCbqriCapacityState *cc = RISCV_CBQRI_CC(dev);
>> > +
>> > +    if (!cc->mmio_base) {
>> > +        error_setg(errp, "mmio_base property not set");
>> > +        return;
>> > +    }
>> > +
>> > +    assert(cc->mon_counters == NULL);
>> > +    cc->mon_counters = g_new0(MonitorCounter, cc->nb_mcids);
>> > +
>> > +    assert(cc->alloc_blockmasks == NULL);
>> > +    uint64_t *end = get_blockmask_location(cc, cc->nb_rcids, 0);
>> > +    unsigned int blockmasks_size = end - cc->alloc_blockmasks;
>> > +    cc->alloc_blockmasks = g_new0(uint64_t, blockmasks_size);
>> > +
>> > +    memory_region_init_io(&cc->mmio, OBJECT(dev), &riscv_cbqri_cc_ops,
>> > +                          cc, TYPE_RISCV_CBQRI_CC".mmio", 4 * 1024);
>> 
>> Shouldn't the region size take cc->ncblks into account?
>> (A bitmask for 2^16 ids is 8kB.)
>
> cc_block_mask field is BMW / 8. In the case of NCBLKS of 12 and NCBLKS
> of 16, both end up with a BMW of 64 which would be 8 bytes. I think the
> the only reason the allocation is 4KB is that is meant to be aligned to
> the page size. Otherwise, the capacity controller register layout is
> pretty small.

I understood NCBLKS as the amount of bits in the capacity bitmask, and
NCBLKS in encoded in a 16 bit field, which means up to 65536 bits.
Is there a lower limit?

Thanks.