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Mon, 24 Nov 2025 09:03:11 -0800 (PST) Received: from localhost ([2a02:8308:a00c:e200::3052]) by smtp.gmail.com with UTF8SMTPSA id ffacd0b85a97d-42cb7f34fd1sm30111795f8f.11.2025.11.24.09.03.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Nov 2025 09:03:10 -0800 (PST) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Mon, 24 Nov 2025 18:02:37 +0100 Message-Id: Subject: Re: [PATCH 3/7] hw/riscv: implement CBQRI capacity controller Cc: , "Palmer Dabbelt" , "Alistair Francis" , "Weiwei Li" , "Daniel Henrique Barboza" , "Liu Zhiwei" , , "Paolo Bonzini" , "Nicolas Pitre" , =?utf-8?q?Kornel_Dul=C4=99ba?= , "Atish Kumar Patra" , "Atish Patra" , "Vasudevan Srinivasan" , "yunhui cui" , "Chen Pei" , , , To: "Drew Fustini" From: =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= References: <20251119-riscv-ssqosid-cbqri-v1-0-3392fc760e48@kernel.org> <20251119-riscv-ssqosid-cbqri-v1-3-3392fc760e48@kernel.org> In-Reply-To: Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=rkrcmar@ventanamicro.com; helo=mail-wm1-x330.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.999, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org 2025-11-21T11:50:50-08:00, Drew Fustini : > On Thu, Nov 20, 2025 at 08:25:44PM +0100, Radim Kr=C4=8Dm=C3=A1=C5=99 wro= te: >> 2025-11-19T16:42:19-08:00, Drew Fustini : >> > +static void riscv_cbqri_cc_realize(DeviceState *dev, Error **errp) >> > +{ >> > + RiscvCbqriCapacityState *cc =3D RISCV_CBQRI_CC(dev); >> > + >> > + if (!cc->mmio_base) { >> > + error_setg(errp, "mmio_base property not set"); >> > + return; >> > + } >> > + >> > + assert(cc->mon_counters =3D=3D NULL); >> > + cc->mon_counters =3D g_new0(MonitorCounter, cc->nb_mcids); >> > + >> > + assert(cc->alloc_blockmasks =3D=3D NULL); >> > + uint64_t *end =3D get_blockmask_location(cc, cc->nb_rcids, 0); >> > + unsigned int blockmasks_size =3D end - cc->alloc_blockmasks; >> > + cc->alloc_blockmasks =3D g_new0(uint64_t, blockmasks_size); >> > + >> > + memory_region_init_io(&cc->mmio, OBJECT(dev), &riscv_cbqri_cc_ops= , >> > + cc, TYPE_RISCV_CBQRI_CC".mmio", 4 * 1024); >>=20 >> Shouldn't the region size take cc->ncblks into account? >> (A bitmask for 2^16 ids is 8kB.) > > cc_block_mask field is BMW / 8. In the case of NCBLKS of 12 and NCBLKS > of 16, both end up with a BMW of 64 which would be 8 bytes. I think the > the only reason the allocation is 4KB is that is meant to be aligned to > the page size. Otherwise, the capacity controller register layout is > pretty small. I understood NCBLKS as the amount of bits in the capacity bitmask, and NCBLKS in encoded in a 16 bit field, which means up to 65536 bits. Is there a lower limit? Thanks.