From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by monty-python.gnu.org with tmda-scanned (Exim 4.24) id 1ANyYy-00074r-Ca for qemu-devel@nongnu.org; Sun, 23 Nov 2003 13:02:24 -0500 Received: from mail by monty-python.gnu.org with spam-scanned (Exim 4.24) id 1ANyY8-0005Jq-TZ for qemu-devel@nongnu.org; Sun, 23 Nov 2003 13:02:04 -0500 Received: from [199.232.41.2] (helo=subversions.gnu.org) by monty-python.gnu.org with esmtp (TLSv1:DES-CBC3-SHA:168) (Exim 4.24) id 1ANyXt-00057U-4Q for qemu-devel@nongnu.org; Sun, 23 Nov 2003 13:01:17 -0500 Received: from bellard by subversions.gnu.org with local (Exim 4.20) id 1ANxYm-0006DX-Cp for qemu-devel@nongnu.org; Sun, 23 Nov 2003 11:58:08 -0500 Message-Id: From: Fabrice Bellard Date: Sun, 23 Nov 2003 11:58:08 -0500 Subject: [Qemu-devel] qemu/target-ppc cpu.h op.c translate.c op_templ... Reply-To: fabrice.bellard@free.fr, qemu-devel@nongnu.org List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org CVSROOT: /cvsroot/qemu Module name: qemu Branch: Changes by: Fabrice Bellard 03/11/23 11:58:08 Modified files: target-ppc : cpu.h op.c translate.c Added files: target-ppc : op_template.h Removed files: target-ppc : op.tpl Log message: suppressed use of gen_multi - use intermediate FT0 register for floats - use T0 temporary for fpscr update - use PARAM1 for spr access - added untested single load/store support CVSWeb URLs: http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/target-ppc/op_template.h?rev=1.1 http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/target-ppc/cpu.h.diff?tr1=1.1&tr2=1.2&r1=text&r2=text http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/target-ppc/op.c.diff?tr1=1.1&tr2=1.2&r1=text&r2=text http://savannah.gnu.org/cgi-bin/viewcvs/qemu/qemu/target-ppc/translate.c.diff?tr1=1.1&tr2=1.2&r1=text&r2=text