* [Qemu-devel] qemu hw/mips_r4k.c target-mips/cpu.h target-mip...
@ 2006-12-06 17:48 Thiemo Seufer
0 siblings, 0 replies; 8+ messages in thread
From: Thiemo Seufer @ 2006-12-06 17:48 UTC (permalink / raw)
To: qemu-devel
CVSROOT: /sources/qemu
Module name: qemu
Changes by: Thiemo Seufer <ths> 06/12/06 17:48:53
Modified files:
hw : mips_r4k.c
target-mips : cpu.h translate.c
Log message:
Halt/reboot support for Linux, by Daniel Jacobowitz. This is a band-aid
until we emulate real MIPS hardware with real firmware.
CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/hw/mips_r4k.c?cvsroot=qemu&r1=1.21&r2=1.22
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/cpu.h?cvsroot=qemu&r1=1.11&r2=1.12
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/translate.c?cvsroot=qemu&r1=1.18&r2=1.19
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Qemu-devel] qemu hw/mips_r4k.c target-mips/cpu.h target-mip...
@ 2006-12-21 1:19 Thiemo Seufer
2006-12-21 9:45 ` Fabrice Bellard
0 siblings, 1 reply; 8+ messages in thread
From: Thiemo Seufer @ 2006-12-21 1:19 UTC (permalink / raw)
To: qemu-devel
CVSROOT: /sources/qemu
Module name: qemu
Changes by: Thiemo Seufer <ths> 06/12/21 01:19:56
Modified files:
hw : mips_r4k.c
target-mips : cpu.h exec.h fop_template.c helper.c
mips-defs.h op.c op_helper.c op_helper_mem.c
op_mem.c op_template.c translate.c
Log message:
Preliminiary MIPS64 support, disabled by default due to performance impact.
CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/hw/mips_r4k.c?cvsroot=qemu&r1=1.24&r2=1.25
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/cpu.h?cvsroot=qemu&r1=1.13&r2=1.14
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/exec.h?cvsroot=qemu&r1=1.12&r2=1.13
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/fop_template.c?cvsroot=qemu&r1=1.1&r2=1.2
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/helper.c?cvsroot=qemu&r1=1.19&r2=1.20
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/mips-defs.h?cvsroot=qemu&r1=1.5&r2=1.6
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op.c?cvsroot=qemu&r1=1.16&r2=1.17
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op_helper.c?cvsroot=qemu&r1=1.20&r2=1.21
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op_helper_mem.c?cvsroot=qemu&r1=1.3&r2=1.4
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op_mem.c?cvsroot=qemu&r1=1.4&r2=1.5
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op_template.c?cvsroot=qemu&r1=1.1&r2=1.2
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/translate.c?cvsroot=qemu&r1=1.28&r2=1.29
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Qemu-devel] qemu hw/mips_r4k.c target-mips/cpu.h target-mip...
2006-12-21 1:19 Thiemo Seufer
@ 2006-12-21 9:45 ` Fabrice Bellard
2006-12-21 11:32 ` Thiemo Seufer
0 siblings, 1 reply; 8+ messages in thread
From: Fabrice Bellard @ 2006-12-21 9:45 UTC (permalink / raw)
To: ths; +Cc: qemu-devel
You should suppress the SIGN_EXTEND32() macro and just use an 'int32_t'
cast...
Fabrice.
Thiemo Seufer wrote:
> CVSROOT: /sources/qemu
> Module name: qemu
> Changes by: Thiemo Seufer <ths> 06/12/21 01:19:56
>
> Modified files:
> hw : mips_r4k.c
> target-mips : cpu.h exec.h fop_template.c helper.c
> mips-defs.h op.c op_helper.c op_helper_mem.c
> op_mem.c op_template.c translate.c
>
> Log message:
> Preliminiary MIPS64 support, disabled by default due to performance impact.
>
> CVSWeb URLs:
> http://cvs.savannah.gnu.org/viewcvs/qemu/hw/mips_r4k.c?cvsroot=qemu&r1=1.24&r2=1.25
> http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/cpu.h?cvsroot=qemu&r1=1.13&r2=1.14
> http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/exec.h?cvsroot=qemu&r1=1.12&r2=1.13
> http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/fop_template.c?cvsroot=qemu&r1=1.1&r2=1.2
> http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/helper.c?cvsroot=qemu&r1=1.19&r2=1.20
> http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/mips-defs.h?cvsroot=qemu&r1=1.5&r2=1.6
> http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op.c?cvsroot=qemu&r1=1.16&r2=1.17
> http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op_helper.c?cvsroot=qemu&r1=1.20&r2=1.21
> http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op_helper_mem.c?cvsroot=qemu&r1=1.3&r2=1.4
> http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op_mem.c?cvsroot=qemu&r1=1.4&r2=1.5
> http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op_template.c?cvsroot=qemu&r1=1.1&r2=1.2
> http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/translate.c?cvsroot=qemu&r1=1.28&r2=1.29
>
>
> _______________________________________________
> Qemu-devel mailing list
> Qemu-devel@nongnu.org
> http://lists.nongnu.org/mailman/listinfo/qemu-devel
>
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Qemu-devel] qemu hw/mips_r4k.c target-mips/cpu.h target-mip...
2006-12-21 9:45 ` Fabrice Bellard
@ 2006-12-21 11:32 ` Thiemo Seufer
2006-12-21 12:45 ` Thiemo Seufer
2006-12-21 14:46 ` André Braga
0 siblings, 2 replies; 8+ messages in thread
From: Thiemo Seufer @ 2006-12-21 11:32 UTC (permalink / raw)
To: Fabrice Bellard; +Cc: qemu-devel
Fabrice Bellard wrote:
> You should suppress the SIGN_EXTEND32() macro and just use an 'int32_t'
> cast...
Then it may not work. A MIPS64 CPU requires properly sign-extended
32bit values. Host architectures can define either sign- or zero-
Extension for 32bit values in 64bit Registers.
Thiemo
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Qemu-devel] qemu hw/mips_r4k.c target-mips/cpu.h target-mip...
2006-12-21 11:32 ` Thiemo Seufer
@ 2006-12-21 12:45 ` Thiemo Seufer
2006-12-21 14:46 ` André Braga
1 sibling, 0 replies; 8+ messages in thread
From: Thiemo Seufer @ 2006-12-21 12:45 UTC (permalink / raw)
To: Fabrice Bellard; +Cc: qemu-devel
Thiemo Seufer wrote:
> Fabrice Bellard wrote:
> > You should suppress the SIGN_EXTEND32() macro and just use an 'int32_t'
> > cast...
>
> Then it may not work. A MIPS64 CPU requires properly sign-extended
> 32bit values. Host architectures can define either sign- or zero-
> Extension for 32bit values in 64bit Registers.
Which makes no sense on a seond thought, as we support only 2-complement
machines anyway. I'll try to get rid of the SIGN_EXTEND32.
Thiemo
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Qemu-devel] qemu hw/mips_r4k.c target-mips/cpu.h target-mip...
2006-12-21 11:32 ` Thiemo Seufer
2006-12-21 12:45 ` Thiemo Seufer
@ 2006-12-21 14:46 ` André Braga
2006-12-21 15:27 ` Thiemo Seufer
1 sibling, 1 reply; 8+ messages in thread
From: André Braga @ 2006-12-21 14:46 UTC (permalink / raw)
To: qemu-devel
On 12/21/06, Thiemo Seufer <ths@networkno.de> wrote:
> Fabrice Bellard wrote:
> > You should suppress the SIGN_EXTEND32() macro and just use an 'int32_t'
> > cast...
>
> Then it may not work. A MIPS64 CPU requires properly sign-extended
> 32bit values. Host architectures can define either sign- or zero-
> Extension for 32bit values in 64bit Registers.
Whether or not it works, GCC *WILL* optimize it away as a redundant
statement, if it deems so (i.e., if it's called with some flag that
enables cse/gcse and peephole optimizations, and the variable(s) in
question is(are) not declared volatile).
IMHO macros like these SHOULD stay, as they are mostly innocuous and
happen to document the target machine behaviour.
Cheers,
A.
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Qemu-devel] qemu hw/mips_r4k.c target-mips/cpu.h target-mip...
2006-12-21 14:46 ` André Braga
@ 2006-12-21 15:27 ` Thiemo Seufer
0 siblings, 0 replies; 8+ messages in thread
From: Thiemo Seufer @ 2006-12-21 15:27 UTC (permalink / raw)
To: qemu-devel
André Braga wrote:
> On 12/21/06, Thiemo Seufer <ths@networkno.de> wrote:
> >Fabrice Bellard wrote:
> >> You should suppress the SIGN_EXTEND32() macro and just use an 'int32_t'
> >> cast...
> >
> >Then it may not work. A MIPS64 CPU requires properly sign-extended
> >32bit values. Host architectures can define either sign- or zero-
> >Extension for 32bit values in 64bit Registers.
>
> Whether or not it works, GCC *WILL* optimize it away as a redundant
> statement,
Only iff it is redundant, which is what we want to achieve.
> if it deems so (i.e., if it's called with some flag that
> enables cse/gcse and peephole optimizations, and the variable(s) in
> question is(are) not declared volatile).
Currently it appears to work as is. Given that the CPU env is a global
it is unlikely gcc can use fancy optimizations. When compiling with
-combine we may need to declare the emulated machine registers volatile.
> IMHO macros like these SHOULD stay, as they are mostly innocuous and
> happen to document the target machine behaviour.
I disagree, it clutters the source more, and a cast provides the same
information.
Thiemo
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Qemu-devel] qemu hw/mips_r4k.c target-mips/cpu.h target-mip...
@ 2006-12-21 13:48 Thiemo Seufer
0 siblings, 0 replies; 8+ messages in thread
From: Thiemo Seufer @ 2006-12-21 13:48 UTC (permalink / raw)
To: qemu-devel
CVSROOT: /sources/qemu
Module name: qemu
Changes by: Thiemo Seufer <ths> 06/12/21 13:48:28
Modified files:
hw : mips_r4k.c
target-mips : cpu.h helper.c op.c op_helper.c translate.c
Log message:
Scrap SIGN_EXTEND32.
CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/hw/mips_r4k.c?cvsroot=qemu&r1=1.25&r2=1.26
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/cpu.h?cvsroot=qemu&r1=1.14&r2=1.15
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/helper.c?cvsroot=qemu&r1=1.20&r2=1.21
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op.c?cvsroot=qemu&r1=1.17&r2=1.18
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op_helper.c?cvsroot=qemu&r1=1.21&r2=1.22
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/translate.c?cvsroot=qemu&r1=1.29&r2=1.30
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2006-12-21 15:37 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
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2006-12-06 17:48 [Qemu-devel] qemu hw/mips_r4k.c target-mips/cpu.h target-mip Thiemo Seufer
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2006-12-21 1:19 Thiemo Seufer
2006-12-21 9:45 ` Fabrice Bellard
2006-12-21 11:32 ` Thiemo Seufer
2006-12-21 12:45 ` Thiemo Seufer
2006-12-21 14:46 ` André Braga
2006-12-21 15:27 ` Thiemo Seufer
2006-12-21 13:48 Thiemo Seufer
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