From: Thiemo Seufer <ths@networkno.de>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] qemu/target-mips cpu.h exec.h op.c op_helper.c ...
Date: Fri, 18 May 2007 11:55:54 +0000 [thread overview]
Message-ID: <E1Hp13q-0000Ib-Hq@cvs> (raw)
CVSROOT: /sources/qemu
Module name: qemu
Changes by: Thiemo Seufer <ths> 07/05/18 11:55:54
Modified files:
target-mips : cpu.h exec.h op.c op_helper.c translate.c
Log message:
- Move FPU exception handling into helper functions, since they are big.
- Fix FP-conditional branches.
- Check FPU register mode at runtime, not translation time, as the F64
status bit can change.
CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/cpu.h?cvsroot=qemu&r1=1.33&r2=1.34
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/exec.h?cvsroot=qemu&r1=1.27&r2=1.28
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op.c?cvsroot=qemu&r1=1.56&r2=1.57
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op_helper.c?cvsroot=qemu&r1=1.46&r2=1.47
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/translate.c?cvsroot=qemu&r1=1.79&r2=1.80
next reply other threads:[~2007-05-18 12:04 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-05-18 11:55 Thiemo Seufer [this message]
-- strict thread matches above, loose matches on Subject: below --
2007-03-23 0:43 [Qemu-devel] qemu/target-mips cpu.h exec.h op.c op_helper.c Thiemo Seufer
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