[Qemu-devel] qemu cpu-defs.h cpu-exec.c exec-all.h exec.c so...

[Qemu-devel] qemu cpu-defs.h cpu-exec.c exec-all.h exec.c so...

[Jocelyn Mayer]

CVSROOT:	/sources/qemu
Module name:	qemu
Changes by:	Jocelyn Mayer <j_mayer>	07/10/14 07:07:08

Modified files:
	.              : cpu-defs.h cpu-exec.c exec-all.h exec.c 
	                 softmmu_exec.h softmmu_header.h 
	                 softmmu_template.h 
	hw             : alpha_palcode.c 
	target-alpha   : cpu.h exec.h helper.c op_helper.c 
	target-arm     : cpu.h exec.h helper.c op_helper.c 
	target-cris    : cpu.h exec.h helper.c mmu.c mmu.h op_helper.c 
	target-i386    : cpu.h exec.h helper.c helper2.c 
	target-m68k    : cpu.h exec.h helper.c op_helper.c 
	target-mips    : cpu.h exec.h helper.c op_helper.c 
	target-ppc     : cpu.h exec.h helper.c op_helper.c translate.c 
	target-sh4     : cpu.h exec.h helper.c op_helper.c 
	target-sparc   : cpu.h exec.h helper.c op_helper.c translate.c 

Log message:
	Replace is_user variable with mmu_idx in softmmu core,
	  allowing support of more than 2 mmu access modes.
	Add backward compatibility is_user variable in targets code when needed.
	Implement per target cpu_mmu_index function, avoiding duplicated code
	  and #ifdef TARGET_xxx in softmmu core functions.
	Implement per target mmu modes definitions. As an example, add PowerPC
	  hypervisor mode definition and Alpha executive and kernel modes definitions.
	Optimize PowerPC case, precomputing mmu_idx when MSR register changes
	  and using the same definition in code translation code.

CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/cpu-defs.h?cvsroot=qemu&r1=1.24&r2=1.25
http://cvs.savannah.gnu.org/viewcvs/qemu/cpu-exec.c?cvsroot=qemu&r1=1.119&r2=1.120
http://cvs.savannah.gnu.org/viewcvs/qemu/exec-all.h?cvsroot=qemu&r1=1.67&r2=1.68
http://cvs.savannah.gnu.org/viewcvs/qemu/exec.c?cvsroot=qemu&r1=1.108&r2=1.109
http://cvs.savannah.gnu.org/viewcvs/qemu/softmmu_exec.h?cvsroot=qemu&r1=1.1&r2=1.2
http://cvs.savannah.gnu.org/viewcvs/qemu/softmmu_header.h?cvsroot=qemu&r1=1.17&r2=1.18
http://cvs.savannah.gnu.org/viewcvs/qemu/softmmu_template.h?cvsroot=qemu&r1=1.18&r2=1.19
http://cvs.savannah.gnu.org/viewcvs/qemu/hw/alpha_palcode.c?cvsroot=qemu&r1=1.3&r2=1.4
http://cvs.savannah.gnu.org/viewcvs/qemu/target-alpha/cpu.h?cvsroot=qemu&r1=1.8&r2=1.9
http://cvs.savannah.gnu.org/viewcvs/qemu/target-alpha/exec.h?cvsroot=qemu&r1=1.3&r2=1.4
http://cvs.savannah.gnu.org/viewcvs/qemu/target-alpha/helper.c?cvsroot=qemu&r1=1.4&r2=1.5
http://cvs.savannah.gnu.org/viewcvs/qemu/target-alpha/op_helper.c?cvsroot=qemu&r1=1.2&r2=1.3
http://cvs.savannah.gnu.org/viewcvs/qemu/target-arm/cpu.h?cvsroot=qemu&r1=1.35&r2=1.36
http://cvs.savannah.gnu.org/viewcvs/qemu/target-arm/exec.h?cvsroot=qemu&r1=1.13&r2=1.14
http://cvs.savannah.gnu.org/viewcvs/qemu/target-arm/helper.c?cvsroot=qemu&r1=1.22&r2=1.23
http://cvs.savannah.gnu.org/viewcvs/qemu/target-arm/op_helper.c?cvsroot=qemu&r1=1.6&r2=1.7
http://cvs.savannah.gnu.org/viewcvs/qemu/target-cris/cpu.h?cvsroot=qemu&r1=1.1&r2=1.2
http://cvs.savannah.gnu.org/viewcvs/qemu/target-cris/exec.h?cvsroot=qemu&r1=1.1&r2=1.2
http://cvs.savannah.gnu.org/viewcvs/qemu/target-cris/helper.c?cvsroot=qemu&r1=1.1&r2=1.2
http://cvs.savannah.gnu.org/viewcvs/qemu/target-cris/mmu.c?cvsroot=qemu&r1=1.1&r2=1.2
http://cvs.savannah.gnu.org/viewcvs/qemu/target-cris/mmu.h?cvsroot=qemu&r1=1.1&r2=1.2
http://cvs.savannah.gnu.org/viewcvs/qemu/target-cris/op_helper.c?cvsroot=qemu&r1=1.1&r2=1.2
http://cvs.savannah.gnu.org/viewcvs/qemu/target-i386/cpu.h?cvsroot=qemu&r1=1.50&r2=1.51
http://cvs.savannah.gnu.org/viewcvs/qemu/target-i386/exec.h?cvsroot=qemu&r1=1.37&r2=1.38
http://cvs.savannah.gnu.org/viewcvs/qemu/target-i386/helper.c?cvsroot=qemu&r1=1.89&r2=1.90
http://cvs.savannah.gnu.org/viewcvs/qemu/target-i386/helper2.c?cvsroot=qemu&r1=1.52&r2=1.53
http://cvs.savannah.gnu.org/viewcvs/qemu/target-m68k/cpu.h?cvsroot=qemu&r1=1.13&r2=1.14
http://cvs.savannah.gnu.org/viewcvs/qemu/target-m68k/exec.h?cvsroot=qemu&r1=1.4&r2=1.5
http://cvs.savannah.gnu.org/viewcvs/qemu/target-m68k/helper.c?cvsroot=qemu&r1=1.7&r2=1.8
http://cvs.savannah.gnu.org/viewcvs/qemu/target-m68k/op_helper.c?cvsroot=qemu&r1=1.6&r2=1.7
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/cpu.h?cvsroot=qemu&r1=1.48&r2=1.49
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/exec.h?cvsroot=qemu&r1=1.38&r2=1.39
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/helper.c?cvsroot=qemu&r1=1.54&r2=1.55
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op_helper.c?cvsroot=qemu&r1=1.65&r2=1.66
http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/cpu.h?cvsroot=qemu&r1=1.79&r2=1.80
http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/exec.h?cvsroot=qemu&r1=1.28&r2=1.29
http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/helper.c?cvsroot=qemu&r1=1.75&r2=1.76
http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.c?cvsroot=qemu&r1=1.49&r2=1.50
http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/translate.c?cvsroot=qemu&r1=1.92&r2=1.93
http://cvs.savannah.gnu.org/viewcvs/qemu/target-sh4/cpu.h?cvsroot=qemu&r1=1.10&r2=1.11
http://cvs.savannah.gnu.org/viewcvs/qemu/target-sh4/exec.h?cvsroot=qemu&r1=1.5&r2=1.6
http://cvs.savannah.gnu.org/viewcvs/qemu/target-sh4/helper.c?cvsroot=qemu&r1=1.4&r2=1.5
http://cvs.savannah.gnu.org/viewcvs/qemu/target-sh4/op_helper.c?cvsroot=qemu&r1=1.4&r2=1.5
http://cvs.savannah.gnu.org/viewcvs/qemu/target-sparc/cpu.h?cvsroot=qemu&r1=1.53&r2=1.54
http://cvs.savannah.gnu.org/viewcvs/qemu/target-sparc/exec.h?cvsroot=qemu&r1=1.21&r2=1.22
http://cvs.savannah.gnu.org/viewcvs/qemu/target-sparc/helper.c?cvsroot=qemu&r1=1.27&r2=1.28
http://cvs.savannah.gnu.org/viewcvs/qemu/target-sparc/op_helper.c?cvsroot=qemu&r1=1.41&r2=1.42
http://cvs.savannah.gnu.org/viewcvs/qemu/target-sparc/translate.c?cvsroot=qemu&r1=1.74&r2=1.75