[Qemu-devel] qemu gdbstub.c linux-user/main.c linux-user/sig...

[Qemu-devel] qemu gdbstub.c linux-user/main.c linux-user/sig...

[Thiemo Seufer]

CVSROOT:	/sources/qemu
Module name:	qemu
Changes by:	Thiemo Seufer <ths>	08/02/12 21:01:26

Modified files:
	.              : gdbstub.c 
	linux-user     : main.c signal.c syscall.c 
	linux-user/mips: target_signal.h 
	linux-user/mips64: target_signal.h 
	linux-user/mipsn32: target_signal.h 
	target-mips    : cpu.h op.c op_helper.c op_template.c 
	                 translate.c 

Log message:
	Make MIPS MT implementation more cache friendly.

CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/gdbstub.c?cvsroot=qemu&r1=1.73&r2=1.74
http://cvs.savannah.gnu.org/viewcvs/qemu/linux-user/main.c?cvsroot=qemu&r1=1.160&r2=1.161
http://cvs.savannah.gnu.org/viewcvs/qemu/linux-user/signal.c?cvsroot=qemu&r1=1.55&r2=1.56
http://cvs.savannah.gnu.org/viewcvs/qemu/linux-user/syscall.c?cvsroot=qemu&r1=1.163&r2=1.164
http://cvs.savannah.gnu.org/viewcvs/qemu/linux-user/mips/target_signal.h?cvsroot=qemu&r1=1.4&r2=1.5
http://cvs.savannah.gnu.org/viewcvs/qemu/linux-user/mips64/target_signal.h?cvsroot=qemu&r1=1.2&r2=1.3
http://cvs.savannah.gnu.org/viewcvs/qemu/linux-user/mipsn32/target_signal.h?cvsroot=qemu&r1=1.1&r2=1.2
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/cpu.h?cvsroot=qemu&r1=1.56&r2=1.57
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op.c?cvsroot=qemu&r1=1.91&r2=1.92
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op_helper.c?cvsroot=qemu&r1=1.77&r2=1.78
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op_template.c?cvsroot=qemu&r1=1.11&r2=1.12
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/translate.c?cvsroot=qemu&r1=1.121&r2=1.122

[Qemu-devel][BUG][PATCH] Change MIPS register access

[Stefan Weil]

[-- Attachment #1: Type: text/plain, Size: 652 bytes --]

Thiemo Seufer schrieb:
> CVSROOT: /sources/qemu
> Module name: qemu
> Changes by: Thiemo Seufer <ths> 08/02/12 21:01:26
>
> Modified files:
> . : gdbstub.c
> linux-user : main.c signal.c syscall.c
> linux-user/mips: target_signal.h
> linux-user/mips64: target_signal.h
> linux-user/mipsn32: target_signal.h
> target-mips : cpu.h op.c op_helper.c op_template.c
> translate.c
>
> Log message:
> Make MIPS MT implementation more cache friendly.
Appendix mips.patch tries to complete Thiemo's changes.
Please check it and add it to QEMU trunk if it is correct.

I don't have a test scenario which could test the effects
of the patch.

Regards
Stefan Weil


[-- Attachment #2: mips.patch --]
[-- Type: text/x-diff, Size: 2350 bytes --]

Index: target-mips/op.c
===================================================================
--- target-mips/op.c	(revision 4209)
+++ target-mips/op.c	(working copy)
@@ -2300,7 +2300,7 @@
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->gpr[PARAM1][other_tc];
+    T0 = env->gpr[other_tc][PARAM1];
     FORCE_RET();
 }
 
@@ -2308,7 +2308,7 @@
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->LO[PARAM1][other_tc];
+    T0 = env->LO[other_tc][PARAM1];
     FORCE_RET();
 }
 
@@ -2316,7 +2316,7 @@
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->HI[PARAM1][other_tc];
+    T0 = env->HI[other_tc][PARAM1];
     FORCE_RET();
 }
 
@@ -2324,7 +2324,7 @@
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->ACX[PARAM1][other_tc];
+    T0 = env->ACX[other_tc][PARAM1];
     FORCE_RET();
 }
 
@@ -2340,7 +2340,7 @@
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->gpr[PARAM1][other_tc];
+    T0 = env->gpr[other_tc][PARAM1];
     FORCE_RET();
 }
 
@@ -2348,7 +2348,7 @@
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->LO[PARAM1][other_tc];
+    T0 = env->LO[other_tc][PARAM1];
     FORCE_RET();
 }
 
@@ -2356,7 +2356,7 @@
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->HI[PARAM1][other_tc];
+    T0 = env->HI[other_tc][PARAM1];
     FORCE_RET();
 }
 
@@ -2364,7 +2364,7 @@
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->ACX[PARAM1][other_tc];
+    T0 = env->ACX[other_tc][PARAM1];
     FORCE_RET();
 }
 
Index: target-mips/op_template.c
===================================================================
--- target-mips/op_template.c	(revision 4209)
+++ target-mips/op_template.c	(working copy)
@@ -52,13 +52,13 @@
 
 void glue(op_load_srsgpr_T0_gpr, REG) (void)
 {
-    T0 = env->gpr[REG][(env->CP0_SRSCtl >> CP0SRSCtl_PSS) & 0xf];
+    T0 = env->gpr[(env->CP0_SRSCtl >> CP0SRSCtl_PSS) & 0xf][REG];
     FORCE_RET();
 }
 
 void glue(op_store_T0_srsgpr_gpr, REG) (void)
 {
-    env->gpr[REG][(env->CP0_SRSCtl >> CP0SRSCtl_PSS) & 0xf] = T0;
+    env->gpr[(env->CP0_SRSCtl >> CP0SRSCtl_PSS) & 0xf][REG] = T0;
     FORCE_RET();
 }
 #endif