From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1JYVcm-0004h3-Dr for qemu-devel@nongnu.org; Sun, 09 Mar 2008 20:12:16 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1JYVcl-0004gN-Sf for qemu-devel@nongnu.org; Sun, 09 Mar 2008 20:12:16 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1JYVcl-0004gE-PB for qemu-devel@nongnu.org; Sun, 09 Mar 2008 20:12:15 -0400 Received: from savannah.gnu.org ([199.232.41.3] helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1JYVcl-0007VW-Di for qemu-devel@nongnu.org; Sun, 09 Mar 2008 20:12:15 -0400 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.63) (envelope-from ) id 1JYVck-0001JT-OT for qemu-devel@nongnu.org; Mon, 10 Mar 2008 00:12:14 +0000 Received: from aurel32 by cvs.savannah.gnu.org with local (Exim 4.63) (envelope-from ) id 1JYVck-0001JQ-G6 for qemu-devel@nongnu.org; Mon, 10 Mar 2008 00:12:14 +0000 Message-Id: From: Aurelien Jarno Date: Mon, 10 Mar 2008 00:12:14 +0000 Subject: [Qemu-devel] qemu/hw gt64xxx.c Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org CVSROOT: /sources/qemu Module name: qemu Changes by: Aurelien Jarno 08/03/10 00:12:14 Modified files: hw : gt64xxx.c Log message: GT64XXX: fix endianness issues: - Byte swapping for internal GT64XXX registers is controlled by the bit 12 of the Configuration Register and not by the PCI Internal Command register. - The bit 0 of the PCI Internal Command register controls byte swapping for PCI access *except for the internal PCI device*, that is when both bus and device numbers are 0. CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/hw/gt64xxx.c?cvsroot=qemu&r1=1.24&r2=1.25