* [Qemu-devel] [4164] MIPS Magnum R4000 machine
@ 2008-04-07 19:47 Aurelien Jarno
2008-04-07 20:52 ` Paul Brook
2008-04-08 6:38 ` Hervé Poussineau
0 siblings, 2 replies; 4+ messages in thread
From: Aurelien Jarno @ 2008-04-07 19:47 UTC (permalink / raw)
To: qemu-devel
Revision: 4164
http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=4164
Author: aurel32
Date: 2008-04-07 19:47:14 +0000 (Mon, 07 Apr 2008)
Log Message:
-----------
MIPS Magnum R4000 machine
Modified Paths:
--------------
trunk/Makefile.target
trunk/hw/boards.h
trunk/hw/mips.h
trunk/vl.c
Added Paths:
-----------
trunk/hw/mips_jazz.c
trunk/hw/rc4030.c
Modified: trunk/Makefile.target
===================================================================
--- trunk/Makefile.target 2008-04-07 19:46:58 UTC (rev 4163)
+++ trunk/Makefile.target 2008-04-07 19:47:14 UTC (rev 4164)
@@ -559,14 +559,14 @@
OBJS+= pflash_cfi02.o ppc4xx_devs.o ppc405_uc.o ppc405_boards.o
endif
ifeq ($(TARGET_BASE_ARCH), mips)
-OBJS+= mips_r4k.o mips_malta.o mips_pica61.o mips_mipssim.o
-OBJS+= mips_timer.o mips_int.o dma.o vga.o serial.o i8254.o i8259.o
-OBJS+= jazz_led.o
+OBJS+= mips_r4k.o mips_jazz.o mips_malta.o mips_pica61.o mips_mipssim.o
+OBJS+= mips_timer.o mips_int.o dma.o vga.o serial.o i8254.o i8259.o rc4030.o
+OBJS+= g364fb.o jazz_led.o
OBJS+= ide.o gt64xxx.o pckbd.o ps2.o fdc.o mc146818rtc.o usb-uhci.o acpi.o ds1225y.o
-OBJS+= piix_pci.o parallel.o cirrus_vga.o $(SOUND_HW)
+OBJS+= piix_pci.o parallel.o cirrus_vga.o pcspk.o $(SOUND_HW)
OBJS+= mipsnet.o
OBJS+= pflash_cfi01.o
-CPPFLAGS += -DHAS_AUDIO
+CPPFLAGS += -DHAS_AUDIO -DHAS_AUDIO_CHOICE
endif
ifeq ($(TARGET_BASE_ARCH), cris)
OBJS+= etraxfs.o
Modified: trunk/hw/boards.h
===================================================================
--- trunk/hw/boards.h 2008-04-07 19:46:58 UTC (rev 4163)
+++ trunk/hw/boards.h 2008-04-07 19:47:14 UTC (rev 4164)
@@ -36,6 +36,9 @@
/* mips_r4k.c */
extern QEMUMachine mips_machine;
+/* mips_jazz.c */
+extern QEMUMachine mips_magnum_machine;
+
/* mips_malta.c */
extern QEMUMachine mips_malta_machine;
Modified: trunk/hw/mips.h
===================================================================
--- trunk/hw/mips.h 2008-04-07 19:46:58 UTC (rev 4163)
+++ trunk/hw/mips.h 2008-04-07 19:47:14 UTC (rev 4164)
@@ -9,6 +9,11 @@
void *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
void ds1225y_set_protection(void *opaque, int protection);
+/* g364fb.c */
+int g364fb_mm_init(DisplayState *ds,
+ int vram_size, int it_shift,
+ target_phys_addr_t vram_base, target_phys_addr_t ctrl_base);
+
/* mipsnet.c */
void mipsnet_init(int base, qemu_irq irq, NICInfo *nd);
@@ -22,4 +27,7 @@
extern void cpu_mips_clock_init(CPUState *);
extern void cpu_mips_irqctrl_init (void);
+/* rc4030.c */
+qemu_irq *rc4030_init(qemu_irq timer, qemu_irq jazz_bus);
+
#endif
Added: trunk/hw/mips_jazz.c
===================================================================
--- trunk/hw/mips_jazz.c (rev 0)
+++ trunk/hw/mips_jazz.c 2008-04-07 19:47:14 UTC (rev 4164)
@@ -0,0 +1,275 @@
+/*
+ * QEMU MIPS Jazz support
+ *
+ * Copyright (c) 2007-2008 Hervé Poussineau
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hw.h"
+#include "mips.h"
+#include "pc.h"
+#include "isa.h"
+#include "fdc.h"
+#include "sysemu.h"
+#include "audio/audio.h"
+#include "boards.h"
+#include "net.h"
+#include "scsi.h"
+
+extern int nographic;
+
+#ifdef TARGET_WORDS_BIGENDIAN
+#define BIOS_FILENAME "mips_bios.bin"
+#else
+#define BIOS_FILENAME "mipsel_bios.bin"
+#endif
+
+#ifdef TARGET_MIPS64
+#define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffULL)
+#else
+#define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffU)
+#endif
+#define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000))
+
+enum jazz_model_e
+{
+ JAZZ_MAGNUM,
+};
+
+static void main_cpu_reset(void *opaque)
+{
+ CPUState *env = opaque;
+ cpu_reset(env);
+}
+
+static uint32_t rtc_readb(void *opaque, target_phys_addr_t addr)
+{
+ CPUState *env = opaque;
+ return cpu_inw(env, 0x71);
+}
+
+static void rtc_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+{
+ CPUState *env = opaque;
+ cpu_outw(env, 0x71, val & 0xff);
+}
+
+static CPUReadMemoryFunc *rtc_read[3] = {
+ rtc_readb,
+ rtc_readb,
+ rtc_readb,
+};
+
+static CPUWriteMemoryFunc *rtc_write[3] = {
+ rtc_writeb,
+ rtc_writeb,
+ rtc_writeb,
+};
+
+#ifdef HAS_AUDIO
+static void audio_init(qemu_irq *pic)
+{
+ struct soundhw *c;
+ int audio_enabled = 0;
+
+ for (c = soundhw; !audio_enabled && c->name; ++c) {
+ audio_enabled = c->enabled;
+ }
+
+ if (audio_enabled) {
+ AudioState *s;
+
+ s = AUD_init();
+ if (s) {
+ for (c = soundhw; c->name; ++c) {
+ if (c->enabled) {
+ if (c->isa) {
+ c->init.init_isa(s, pic);
+ }
+ }
+ }
+ }
+ }
+}
+#endif
+
+void espdma_memory_read(void *opaque, uint8_t *buf, int len)
+{
+ printf("espdma_memory_read(buf %p, len %d) not implemented\n", buf, len);
+}
+
+void espdma_memory_write(void *opaque, uint8_t *buf, int len)
+{
+ printf("espdma_memory_write(buf %p, len %d) not implemented\n", buf, len);
+}
+
+#define MAGNUM_BIOS_SIZE_MAX 0x7e000
+#define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
+
+static
+void mips_jazz_init (int ram_size, int vga_ram_size,
+ DisplayState *ds, const char *cpu_model,
+ enum jazz_model_e jazz_model)
+{
+ char buf[1024];
+ unsigned long bios_offset;
+ int bios_size, n;
+ CPUState *env;
+ qemu_irq *rc4030, *i8259;
+ void *scsi_hba;
+ int hd;
+ int s_rtc;
+ PITState *pit;
+ BlockDriverState *fds[MAX_FD];
+ qemu_irq esp_reset;
+
+ /* init CPUs */
+ if (cpu_model == NULL) {
+#ifdef TARGET_MIPS64
+ cpu_model = "R4000";
+#else
+ /* FIXME: All wrong, this maybe should be R3000 for the older JAZZs. */
+ cpu_model = "24Kf";
+#endif
+ }
+ env = cpu_init(cpu_model);
+ if (!env) {
+ fprintf(stderr, "Unable to find CPU definition\n");
+ exit(1);
+ }
+ register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
+ qemu_register_reset(main_cpu_reset, env);
+
+ /* allocate RAM */
+ cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
+
+ /* load the BIOS image. */
+ bios_offset = ram_size + vga_ram_size;
+ snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
+ bios_size = load_image(buf, phys_ram_base + bios_offset);
+ if (bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) {
+ fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n",
+ buf);
+ exit(1);
+ }
+
+ cpu_register_physical_memory(0x1fc00000LL,
+ MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM);
+ cpu_register_physical_memory(0xfff00000LL,
+ MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM);
+
+ /* Init CPU internal devices */
+ cpu_mips_irq_init_cpu(env);
+ cpu_mips_clock_init(env);
+
+ /* Chipset */
+ rc4030 = rc4030_init(env->irq[6], env->irq[3]);
+
+ /* ISA devices */
+ i8259 = i8259_init(env->irq[4]);
+ pit = pit_init(0x40, i8259[0]);
+ pcspk_init(pit);
+
+ /* ISA IO space at 0x90000000 */
+ isa_mmio_init(0x90000000, 0x01000000);
+ isa_mem_base = 0x11000000;
+
+ /* Video card */
+ switch (jazz_model) {
+ case JAZZ_MAGNUM:
+ g364fb_mm_init(ds, vga_ram_size, 0, 0x40000000, 0x60000000);
+ break;
+ default:
+ break;
+ }
+
+ /* Network controller */
+ /* FIXME: missing NS SONIC DP83932 */
+
+ /* SCSI adapter */
+ scsi_hba = esp_init(0x80002000,
+ espdma_memory_read, espdma_memory_write, NULL,
+ rc4030[5], &esp_reset);
+ for (n = 0; n < ESP_MAX_DEVS; n++) {
+ hd = drive_get_index(IF_SCSI, 0, n);
+ if (hd != -1) {
+ esp_scsi_attach(scsi_hba, drives_table[hd].bdrv, n);
+ }
+ }
+
+ /* Floppy */
+ if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) {
+ fprintf(stderr, "qemu: too many floppy drives\n");
+ exit(1);
+ }
+ for (n = 0; n < MAX_FD; n++) {
+ int fd = drive_get_index(IF_FLOPPY, 0, n);
+ if (fd != -1)
+ fds[n] = drives_table[fd].bdrv;
+ else
+ fds[n] = NULL;
+ }
+ fdctrl_init(rc4030[1], 0, 1, 0x80003000, fds);
+
+ /* Real time clock */
+ rtc_init(0x70, i8259[8]);
+ s_rtc = cpu_register_io_memory(0, rtc_read, rtc_write, env);
+ cpu_register_physical_memory(0x80004000, 0x00001000, s_rtc);
+
+ /* Keyboard (i8042) */
+ i8042_mm_init(rc4030[6], rc4030[7], 0x80005000, 0);
+
+ /* Serial ports */
+ if (serial_hds[0])
+ serial_mm_init(0x80006000, 0, rc4030[8], serial_hds[0], 1);
+ if (serial_hds[1])
+ serial_mm_init(0x80007000, 0, rc4030[9], serial_hds[1], 1);
+
+ /* Parallel port */
+ if (parallel_hds[0])
+ parallel_mm_init(0x80008000, 0, rc4030[0], parallel_hds[0]);
+
+ /* Sound card */
+ /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
+#ifdef HAS_AUDIO
+ audio_init(i8259);
+#endif
+
+ /* NVRAM: Unprotected at 0x9000, Protected at 0xa000, Read only at 0xb000 */
+ ds1225y_init(0x80009000, "nvram");
+
+ /* LED indicator */
+ jazz_led_init(ds, 0x8000f000);
+}
+
+static
+void mips_magnum_init (int ram_size, int vga_ram_size,
+ const char *boot_device, DisplayState *ds,
+ const char *kernel_filename, const char *kernel_cmdline,
+ const char *initrd_filename, const char *cpu_model)
+{
+ mips_jazz_init(ram_size, vga_ram_size, ds, cpu_model, JAZZ_MAGNUM);
+}
+
+QEMUMachine mips_magnum_machine = {
+ "magnum",
+ "MIPS Magnum",
+ mips_magnum_init,
+};
Added: trunk/hw/rc4030.c
===================================================================
--- trunk/hw/rc4030.c (rev 0)
+++ trunk/hw/rc4030.c 2008-04-07 19:47:14 UTC (rev 4164)
@@ -0,0 +1,608 @@
+/*
+ * QEMU JAZZ RC4030 chipset
+ *
+ * Copyright (c) 2007-2008 Hervé Poussineau
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hw.h"
+#include "qemu-timer.h"
+
+//#define DEBUG_RC4030
+
+#ifdef DEBUG_RC4030
+static const char* irq_names[] = { "parallel", "floppy", "sound", "video",
+ "network", "scsi", "keyboard", "mouse", "serial0", "serial1" };
+#endif
+
+typedef struct rc4030State
+{
+ uint32_t config; /* 0x0000: RC4030 config register */
+ uint32_t invalid_address_register; /* 0x0010: Invalid Address register */
+
+ /* DMA */
+ uint32_t dma_regs[8][4];
+ uint32_t dma_tl_base; /* 0x0018: DMA transl. table base */
+ uint32_t dma_tl_limit; /* 0x0020: DMA transl. table limit */
+
+ /* cache */
+ uint32_t remote_failed_address; /* 0x0038: Remote Failed Address */
+ uint32_t memory_failed_address; /* 0x0040: Memory Failed Address */
+ uint32_t cache_ptag; /* 0x0048: I/O Cache Physical Tag */
+ uint32_t cache_ltag; /* 0x0050: I/O Cache Logical Tag */
+ uint32_t cache_bmask; /* 0x0058: I/O Cache Byte Mask */
+ uint32_t cache_bwin; /* 0x0060: I/O Cache Buffer Window */
+
+ uint32_t offset208;
+ uint32_t offset210;
+ uint32_t nvram_protect; /* 0x0220: NV ram protect register */
+ uint32_t offset238;
+ uint32_t rem_speed[15];
+ uint32_t imr_jazz; /* Local bus int enable mask */
+ uint32_t isr_jazz; /* Local bus int source */
+
+ /* timer */
+ QEMUTimer *periodic_timer;
+ uint32_t itr; /* Interval timer reload */
+
+ uint32_t dummy32;
+ qemu_irq timer_irq;
+ qemu_irq jazz_bus_irq;
+} rc4030State;
+
+static void set_next_tick(rc4030State *s)
+{
+ qemu_irq_lower(s->timer_irq);
+ uint32_t hz;
+
+ hz = 1000 / (s->itr + 1);
+
+ qemu_mod_timer(s->periodic_timer, qemu_get_clock(vm_clock) + ticks_per_sec / hz);
+}
+
+/* called for accesses to rc4030 */
+static uint32_t rc4030_readl(void *opaque, target_phys_addr_t addr)
+{
+ rc4030State *s = opaque;
+ uint32_t val;
+
+ addr &= 0x3fff;
+ switch (addr & ~0x3) {
+ /* Global config register */
+ case 0x0000:
+ val = s->config;
+ break;
+ /* Invalid Address register */
+ case 0x0010:
+ val = s->invalid_address_register;
+ break;
+ /* DMA transl. table base */
+ case 0x0018:
+ val = s->dma_tl_base;
+ break;
+ /* DMA transl. table limit */
+ case 0x0020:
+ val = s->dma_tl_limit;
+ break;
+ /* Remote Failed Address */
+ case 0x0038:
+ val = s->remote_failed_address;
+ break;
+ /* Memory Failed Address */
+ case 0x0040:
+ val = s->memory_failed_address;
+ break;
+ /* I/O Cache Byte Mask */
+ case 0x0058:
+ val = s->cache_bmask;
+ /* HACK */
+ if (s->cache_bmask == (uint32_t)-1)
+ s->cache_bmask = 0;
+ break;
+ /* Remote Speed Registers */
+ case 0x0070:
+ case 0x0078:
+ case 0x0080:
+ case 0x0088:
+ case 0x0090:
+ case 0x0098:
+ case 0x00a0:
+ case 0x00a8:
+ case 0x00b0:
+ case 0x00b8:
+ case 0x00c0:
+ case 0x00c8:
+ case 0x00d0:
+ case 0x00d8:
+ case 0x00e0:
+ val = s->rem_speed[(addr - 0x0070) >> 3];
+ break;
+ /* DMA channel base address */
+ case 0x0100:
+ case 0x0108:
+ case 0x0110:
+ case 0x0118:
+ case 0x0120:
+ case 0x0128:
+ case 0x0130:
+ case 0x0138:
+ case 0x0140:
+ case 0x0148:
+ case 0x0150:
+ case 0x0158:
+ case 0x0160:
+ case 0x0168:
+ case 0x0170:
+ case 0x0178:
+ case 0x0180:
+ case 0x0188:
+ case 0x0190:
+ case 0x0198:
+ case 0x01a0:
+ case 0x01a8:
+ case 0x01b0:
+ case 0x01b8:
+ case 0x01c0:
+ case 0x01c8:
+ case 0x01d0:
+ case 0x01d8:
+ case 0x01e0:
+ case 0x1e8:
+ case 0x01f0:
+ case 0x01f8:
+ {
+ int entry = (addr - 0x0100) >> 5;
+ int idx = (addr & 0x1f) >> 3;
+ val = s->dma_regs[entry][idx];
+ }
+ break;
+ /* Offset 0x0208 */
+ case 0x0208:
+ val = s->offset208;
+ break;
+ /* Offset 0x0210 */
+ case 0x0210:
+ val = s->offset210;
+ break;
+ /* NV ram protect register */
+ case 0x0220:
+ val = s->nvram_protect;
+ break;
+ /* Interval timer count */
+ case 0x0230:
+ val = s->dummy32;
+ qemu_irq_lower(s->timer_irq);
+ break;
+ /* Offset 0x0238 */
+ case 0x0238:
+ val = s->offset238;
+ break;
+ default:
+#ifdef DEBUG_RC4030
+ printf("rc4030: invalid read [" TARGET_FMT_lx "]\n", addr);
+#endif
+ val = 0;
+ break;
+ }
+
+#ifdef DEBUG_RC4030
+ if ((addr & ~3) != 0x230)
+ printf("rc4030: read 0x%02x at " TARGET_FMT_lx "\n", val, addr);
+#endif
+
+ return val;
+}
+
+static uint32_t rc4030_readw(void *opaque, target_phys_addr_t addr)
+{
+ uint32_t v = rc4030_readl(opaque, addr & ~0x3);
+ if (addr & 0x2)
+ return v >> 16;
+ else
+ return v & 0xffff;
+}
+
+static uint32_t rc4030_readb(void *opaque, target_phys_addr_t addr)
+{
+ uint32_t v = rc4030_readl(opaque, addr & ~0x3);
+ return (v >> (8 * (addr & 0x3))) & 0xff;
+}
+
+static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+{
+ rc4030State *s = opaque;
+ addr &= 0x3fff;
+
+#ifdef DEBUG_RC4030
+ printf("rc4030: write 0x%02x at " TARGET_FMT_lx "\n", val, addr);
+#endif
+
+ switch (addr & ~0x3) {
+ /* Global config register */
+ case 0x0000:
+ s->config = val;
+ break;
+ /* DMA transl. table base */
+ case 0x0018:
+ s->dma_tl_base = val;
+ break;
+ /* DMA transl. table limit */
+ case 0x0020:
+ s->dma_tl_limit = val;
+ break;
+ /* I/O Cache Physical Tag */
+ case 0x0048:
+ s->cache_ptag = val;
+ break;
+ /* I/O Cache Logical Tag */
+ case 0x0050:
+ s->cache_ltag = val;
+ break;
+ /* I/O Cache Byte Mask */
+ case 0x0058:
+ s->cache_bmask |= val; /* HACK */
+ break;
+ /* I/O Cache Buffer Window */
+ case 0x0060:
+ s->cache_bwin = val;
+ /* HACK */
+ if (s->cache_ltag == 0x80000001 && s->cache_bmask == 0xf0f0f0f) {
+ target_phys_addr_t dests[] = { 4, 0, 8, 0x10 };
+ static int current = 0;
+ target_phys_addr_t dest = 0 + dests[current];
+ uint8_t buf;
+ current = (current + 1) % (sizeof(dests)/sizeof(dests[0]));
+ buf = s->cache_bwin - 1;
+ cpu_physical_memory_rw(dest, &buf, 1, 1);
+ }
+ break;
+ /* Remote Speed Registers */
+ case 0x0070:
+ case 0x0078:
+ case 0x0080:
+ case 0x0088:
+ case 0x0090:
+ case 0x0098:
+ case 0x00a0:
+ case 0x00a8:
+ case 0x00b0:
+ case 0x00b8:
+ case 0x00c0:
+ case 0x00c8:
+ case 0x00d0:
+ case 0x00d8:
+ case 0x00e0:
+ s->rem_speed[(addr - 0x0070) >> 3] = val;
+ break;
+ /* DMA channel base address */
+ case 0x0100:
+ case 0x0108:
+ case 0x0110:
+ case 0x0118:
+ case 0x0120:
+ case 0x0128:
+ case 0x0130:
+ case 0x0138:
+ case 0x0140:
+ case 0x0148:
+ case 0x0150:
+ case 0x0158:
+ case 0x0160:
+ case 0x0168:
+ case 0x0170:
+ case 0x0178:
+ case 0x0180:
+ case 0x0188:
+ case 0x0190:
+ case 0x0198:
+ case 0x01a0:
+ case 0x01a8:
+ case 0x01b0:
+ case 0x01b8:
+ case 0x01c0:
+ case 0x01c8:
+ case 0x01d0:
+ case 0x01d8:
+ case 0x01e0:
+ case 0x1e8:
+ case 0x01f0:
+ case 0x01f8:
+ {
+ int entry = (addr - 0x0100) >> 5;
+ int idx = (addr & 0x1f) >> 3;
+ s->dma_regs[entry][idx] = val;
+ }
+ break;
+ /* Offset 0x0210 */
+ case 0x0210:
+ s->offset210 = val;
+ break;
+ /* Interval timer reload */
+ case 0x0228:
+ s->itr = val;
+ qemu_irq_lower(s->timer_irq);
+ set_next_tick(s);
+ break;
+ default:
+#ifdef DEBUG_RC4030
+ printf("rc4030: invalid write of 0x%02x at [" TARGET_FMT_lx "]\n", val, addr);
+#endif
+ break;
+ }
+}
+
+static void rc4030_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
+{
+ uint32_t old_val = rc4030_readl(opaque, addr & ~0x3);
+
+ if (addr & 0x2)
+ val = (val << 16) | (old_val & 0x0000ffff);
+ else
+ val = val | (old_val & 0xffff0000);
+ rc4030_writel(opaque, addr & ~0x3, val);
+}
+
+static void rc4030_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+{
+ uint32_t old_val = rc4030_readl(opaque, addr & ~0x3);
+
+ switch (addr & 3) {
+ case 0:
+ val = val | (old_val & 0xffffff00);
+ break;
+ case 1:
+ val = (val << 8) | (old_val & 0xffff00ff);
+ break;
+ case 2:
+ val = (val << 16) | (old_val & 0xff00ffff);
+ break;
+ case 3:
+ val = (val << 24) | (old_val & 0x00ffffff);
+ break;
+ }
+ rc4030_writel(opaque, addr & ~0x3, val);
+}
+
+static CPUReadMemoryFunc *rc4030_read[3] = {
+ rc4030_readb,
+ rc4030_readw,
+ rc4030_readl,
+};
+
+static CPUWriteMemoryFunc *rc4030_write[3] = {
+ rc4030_writeb,
+ rc4030_writew,
+ rc4030_writel,
+};
+
+static void update_jazz_irq(rc4030State *s)
+{
+ uint16_t pending;
+
+ pending = s->isr_jazz & s->imr_jazz;
+
+#ifdef DEBUG_RC4030
+ if (s->isr_jazz != 0) {
+ uint32_t irq = 0;
+ printf("jazz pending:");
+ for (irq = 0; irq < sizeof(irq_names)/sizeof(irq_names[0]); irq++) {
+ if (s->isr_jazz & (1 << irq)) {
+ printf(" %s", irq_names[irq]);
+ if (!(s->imr_jazz & (1 << irq))) {
+ printf("(ignored)");
+ }
+ }
+ }
+ printf("\n");
+ }
+#endif
+
+ if (pending != 0)
+ qemu_irq_raise(s->jazz_bus_irq);
+ else
+ qemu_irq_lower(s->jazz_bus_irq);
+}
+
+static void rc4030_irq_jazz_request(void *opaque, int irq, int level)
+{
+ rc4030State *s = opaque;
+
+ if (level) {
+ s->isr_jazz |= 1 << irq;
+ } else {
+ s->isr_jazz &= ~(1 << irq);
+ }
+
+ update_jazz_irq(s);
+}
+
+static void rc4030_periodic_timer(void *opaque)
+{
+ rc4030State *s = opaque;
+
+ set_next_tick(s);
+ qemu_irq_raise(s->timer_irq);
+}
+
+static uint32_t int_readb(void *opaque, target_phys_addr_t addr)
+{
+ rc4030State *s = opaque;
+ uint32_t val;
+ uint32_t irq;
+ addr &= 0xfff;
+
+ switch (addr) {
+ case 0x00: {
+ /* Local bus int source */
+ uint32_t pending = s->isr_jazz & s->imr_jazz;
+ val = 0;
+ irq = 0;
+ while (pending) {
+ if (pending & 1) {
+ //printf("returning irq %s\n", irq_names[irq]);
+ val = (irq + 1) << 2;
+ break;
+ }
+ irq++;
+ pending >>= 1;
+ }
+ break;
+ }
+ default:
+#ifdef DEBUG_RC4030
+ printf("rc4030: (interrupt controller) invalid read [" TARGET_FMT_lx "]\n", addr);
+#endif
+ val = 0;
+ }
+
+#ifdef DEBUG_RC4030
+ printf("rc4030: (interrupt controller) read 0x%02x at " TARGET_FMT_lx "\n", val, addr);
+#endif
+
+ return val;
+}
+
+static uint32_t int_readw(void *opaque, target_phys_addr_t addr)
+{
+ uint32_t v;
+ v = int_readb(opaque, addr);
+ v |= int_readb(opaque, addr + 1) << 8;
+ return v;
+}
+
+static uint32_t int_readl(void *opaque, target_phys_addr_t addr)
+{
+ uint32_t v;
+ v = int_readb(opaque, addr);
+ v |= int_readb(opaque, addr + 1) << 8;
+ v |= int_readb(opaque, addr + 2) << 16;
+ v |= int_readb(opaque, addr + 3) << 24;
+ return v;
+}
+
+static void int_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+{
+ rc4030State *s = opaque;
+ addr &= 0xfff;
+
+#ifdef DEBUG_RC4030
+ printf("rc4030: (interrupt controller) write 0x%02x at " TARGET_FMT_lx "\n", val, addr);
+#endif
+
+ switch (addr) {
+ /* Local bus int enable mask */
+ case 0x02:
+ s->imr_jazz = (s->imr_jazz & 0xff00) | (val << 0); update_jazz_irq(s);
+ break;
+ case 0x03:
+ s->imr_jazz = (s->imr_jazz & 0x00ff) | (val << 8); update_jazz_irq(s);
+ break;
+ default:
+#ifdef DEBUG_RC4030
+ printf("rc4030: (interrupt controller) invalid write of 0x%02x at [" TARGET_FMT_lx "]\n", val, addr);
+#endif
+ break;
+ }
+}
+
+static void int_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
+{
+ int_writeb(opaque, addr, val & 0xff);
+ int_writeb(opaque, addr + 1, (val >> 8) & 0xff);
+}
+
+static void int_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+{
+ int_writeb(opaque, addr, val & 0xff);
+ int_writeb(opaque, addr + 1, (val >> 8) & 0xff);
+ int_writeb(opaque, addr + 2, (val >> 16) & 0xff);
+ int_writeb(opaque, addr + 3, (val >> 24) & 0xff);
+}
+
+static CPUReadMemoryFunc *int_read[3] = {
+ int_readb,
+ int_readw,
+ int_readl,
+};
+
+static CPUWriteMemoryFunc *int_write[3] = {
+ int_writeb,
+ int_writew,
+ int_writel,
+};
+
+#define G364_512KB_RAM (0x0)
+#define G364_2MB_RAM (0x1)
+#define G364_8MB_RAM (0x2)
+#define G364_32MB_RAM (0x3)
+
+static void rc4030_reset(void *opaque)
+{
+ rc4030State *s = opaque;
+ int i;
+
+ s->config = (G364_2MB_RAM << 8) | 0x04;
+ s->invalid_address_register = 0;
+
+ memset(s->dma_regs, 0, sizeof(s->dma_regs));
+ s->dma_tl_base = s->dma_tl_limit = 0;
+
+ s->remote_failed_address = s->memory_failed_address = 0;
+ s->cache_ptag = s->cache_ltag = 0;
+ s->cache_bmask = s->cache_bwin = 0;
+
+ s->offset208 = 0;
+ s->offset210 = 0x18186;
+ s->nvram_protect = 7;
+ s->offset238 = 7;
+ for (i = 0; i < 15; i++)
+ s->rem_speed[i] = 7;
+ s->imr_jazz = s->isr_jazz = 0;
+
+ s->itr = 0;
+ s->dummy32 = 0;
+
+ qemu_irq_lower(s->timer_irq);
+ qemu_irq_lower(s->jazz_bus_irq);
+}
+
+qemu_irq *rc4030_init(qemu_irq timer, qemu_irq jazz_bus)
+{
+ rc4030State *s;
+ int s_chipset, s_int;
+
+ s = qemu_mallocz(sizeof(rc4030State));
+ if (!s)
+ return NULL;
+
+ s->periodic_timer = qemu_new_timer(vm_clock, rc4030_periodic_timer, s);
+ s->timer_irq = timer;
+ s->jazz_bus_irq = jazz_bus;
+
+ qemu_register_reset(rc4030_reset, s);
+ rc4030_reset(s);
+
+ s_chipset = cpu_register_io_memory(0, rc4030_read, rc4030_write, s);
+ cpu_register_physical_memory(0x80000000, 0x300, s_chipset);
+ s_int = cpu_register_io_memory(0, int_read, int_write, s);
+ cpu_register_physical_memory(0xf0000000, 0x00001000, s_int);
+
+ return qemu_allocate_irqs(rc4030_irq_jazz_request, s, 16);
+}
Modified: trunk/vl.c
===================================================================
--- trunk/vl.c 2008-04-07 19:46:58 UTC (rev 4163)
+++ trunk/vl.c 2008-04-07 19:47:14 UTC (rev 4164)
@@ -26,7 +26,6 @@
#include "hw/usb.h"
#include "hw/pcmcia.h"
#include "hw/pc.h"
-#include "hw/fdc.h"
#include "hw/audiodev.h"
#include "hw/isa.h"
#include "net.h"
@@ -8002,6 +8001,7 @@
qemu_register_machine(&taihu_machine);
#elif defined(TARGET_MIPS)
qemu_register_machine(&mips_machine);
+ qemu_register_machine(&mips_magnum_machine);
qemu_register_machine(&mips_malta_machine);
qemu_register_machine(&mips_pica61_machine);
qemu_register_machine(&mips_mipssim_machine);
@@ -8056,7 +8056,7 @@
#ifdef HAS_AUDIO
struct soundhw soundhw[] = {
#ifdef HAS_AUDIO_CHOICE
-#ifdef TARGET_I386
+#if defined(TARGET_I386) || defined(TARGET_MIPS)
{
"pcspk",
"PC speaker",
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Qemu-devel] [4164] MIPS Magnum R4000 machine
2008-04-07 19:47 [Qemu-devel] [4164] MIPS Magnum R4000 machine Aurelien Jarno
@ 2008-04-07 20:52 ` Paul Brook
2008-04-08 6:38 ` Hervé Poussineau
1 sibling, 0 replies; 4+ messages in thread
From: Paul Brook @ 2008-04-07 20:52 UTC (permalink / raw)
To: qemu-devel; +Cc: Aurelien Jarno
> Log Message:
> -----------
> MIPS Magnum R4000 machine
You also need to add documentation.
Paul
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Qemu-devel] [4164] MIPS Magnum R4000 machine
2008-04-07 19:47 [Qemu-devel] [4164] MIPS Magnum R4000 machine Aurelien Jarno
2008-04-07 20:52 ` Paul Brook
@ 2008-04-08 6:38 ` Hervé Poussineau
2008-04-08 8:01 ` Aurelien Jarno
1 sibling, 1 reply; 4+ messages in thread
From: Hervé Poussineau @ 2008-04-08 6:38 UTC (permalink / raw)
To: qemu-devel
Aurelien Jarno a écrit :
> Revision: 4164
> http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=4164
> Author: aurel32
> Date: 2008-04-07 19:47:14 +0000 (Mon, 07 Apr 2008)
>
> Log Message:
> -----------
> MIPS Magnum R4000 machine
>
> Added Paths:
> -----------
> trunk/hw/mips_jazz.c
> trunk/hw/rc4030.c
>
Please be consistent.
The added files are encoded in unicode, whereas existing ones are not.
Also, diff.exe on Windows (provided with MSYS) considers unicode files
as binary, which means that I can't provide patches for them...
Hervé
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Qemu-devel] [4164] MIPS Magnum R4000 machine
2008-04-08 6:38 ` Hervé Poussineau
@ 2008-04-08 8:01 ` Aurelien Jarno
0 siblings, 0 replies; 4+ messages in thread
From: Aurelien Jarno @ 2008-04-08 8:01 UTC (permalink / raw)
To: qemu-devel
Hervé Poussineau a écrit :
> Aurelien Jarno a écrit :
>> Revision: 4164
>> http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=4164
>> Author: aurel32
>> Date: 2008-04-07 19:47:14 +0000 (Mon, 07 Apr 2008)
>>
>> Log Message:
>> -----------
>> MIPS Magnum R4000 machine
> >
>> Added Paths:
>> -----------
>> trunk/hw/mips_jazz.c
>> trunk/hw/rc4030.c
>>
>
> Please be consistent.
> The added files are encoded in unicode, whereas existing ones are not.
Wrong they are not encoded in unicode (should be UTF-16 from your
description on IRC), but in UTF-8. It's your software which convert them
to UTF-16.
Also a few other files are *already* encoded in UTF-8 in the SVN.
> Also, diff.exe on Windows (provided with MSYS) considers unicode files
> as binary, which means that I can't provide patches for them...
Then you software is buggy.
The only workaround I can see from the software point of view is to
remove the accents from you name in those files, so that they are
changed to plain ASCII. But in that case, please don't submit patches
with non-ASCII chars. Also I won't change other files already in UTF-8.
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2008-04-08 8:02 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2008-04-07 19:47 [Qemu-devel] [4164] MIPS Magnum R4000 machine Aurelien Jarno
2008-04-07 20:52 ` Paul Brook
2008-04-08 6:38 ` Hervé Poussineau
2008-04-08 8:01 ` Aurelien Jarno
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