* [Qemu-devel] [4242] Fix PHYS_ADDR_MASK: upper bits of a PTE are reserved so they are 52 bits
@ 2008-04-22 21:57 Aurelien Jarno
0 siblings, 0 replies; only message in thread
From: Aurelien Jarno @ 2008-04-22 21:57 UTC (permalink / raw)
To: qemu-devel
Revision: 4242
http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=4242
Author: aurel32
Date: 2008-04-22 21:57:57 +0000 (Tue, 22 Apr 2008)
Log Message:
-----------
Fix PHYS_ADDR_MASK: upper bits of a PTE are reserved so they are 52 bits
long. Thanks to Paul Brook for noticing that.
Modified Paths:
--------------
trunk/target-i386/helper2.c
Modified: trunk/target-i386/helper2.c
===================================================================
--- trunk/target-i386/helper2.c 2008-04-22 20:45:30 UTC (rev 4241)
+++ trunk/target-i386/helper2.c 2008-04-22 21:57:57 UTC (rev 4242)
@@ -800,7 +800,8 @@
#else
-#define PHYS_ADDR_MASK (~0xfff)
+/* Bits 52-62 of a PTE are reserved. Bit 63 is the NX bit. */
+#define PHYS_ADDR_MASK 0xffffffffff000L
/* return value:
-1 = cannot handle fault
^ permalink raw reply [flat|nested] only message in thread
only message in thread, other threads:[~2008-04-22 21:58 UTC | newest]
Thread overview: (only message) (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2008-04-22 21:57 [Qemu-devel] [4242] Fix PHYS_ADDR_MASK: upper bits of a PTE are reserved so they are 52 bits Aurelien Jarno
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).