From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1JoiWN-0007bq-LQ for qemu-devel@nongnu.org; Wed, 23 Apr 2008 13:12:39 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1JoiWN-0007bW-2c for qemu-devel@nongnu.org; Wed, 23 Apr 2008 13:12:39 -0400 Received: from [199.232.76.173] (port=45821 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1JoiWM-0007bO-No for qemu-devel@nongnu.org; Wed, 23 Apr 2008 13:12:38 -0400 Received: from savannah.gnu.org ([199.232.41.3] helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1JoiWM-0002vO-Fg for qemu-devel@nongnu.org; Wed, 23 Apr 2008 13:12:38 -0400 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.63) (envelope-from ) id 1JoiWL-0002IN-Ty for qemu-devel@nongnu.org; Wed, 23 Apr 2008 17:12:38 +0000 Received: from blueswir1 by cvs.savannah.gnu.org with local (Exim 4.63) (envelope-from ) id 1JoiWL-0002IB-Bd for qemu-devel@nongnu.org; Wed, 23 Apr 2008 17:12:37 +0000 MIME-Version: 1.0 Errors-To: blueswir1 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Blue Swirl Message-Id: Date: Wed, 23 Apr 2008 17:12:37 +0000 Subject: [Qemu-devel] [4243] Document the shift values Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 4243 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=4243 Author: blueswir1 Date: 2008-04-23 17:12:35 +0000 (Wed, 23 Apr 2008) Log Message: ----------- Document the shift values Modified Paths: -------------- trunk/target-sparc/cpu.h trunk/target-sparc/translate.c Modified: trunk/target-sparc/cpu.h =================================================================== --- trunk/target-sparc/cpu.h 2008-04-22 21:57:57 UTC (rev 4242) +++ trunk/target-sparc/cpu.h 2008-04-23 17:12:35 UTC (rev 4243) @@ -71,10 +71,14 @@ #define TT_TRAP 0x100 #endif -#define PSR_NEG (1<<23) -#define PSR_ZERO (1<<22) -#define PSR_OVF (1<<21) -#define PSR_CARRY (1<<20) +#define PSR_NEG_SHIFT 23 +#define PSR_NEG (1 << PSR_NEG_SHIFT) +#define PSR_ZERO_SHIFT 22 +#define PSR_ZERO (1 << PSR_ZERO_SHIFT) +#define PSR_OVF_SHIFT 21 +#define PSR_OVF (1 << PSR_OVF_SHIFT) +#define PSR_CARRY_SHIFT 20 +#define PSR_CARRY (1 << PSR_CARRY_SHIFT) #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY) #define PSR_EF (1<<12) #define PSR_PIL 0xf00 @@ -141,8 +145,10 @@ #define FSR_FTT_SEQ_ERROR (4 << 14) #define FSR_FTT_INVAL_FPR (6 << 14) -#define FSR_FCC1 (1<<11) -#define FSR_FCC0 (1<<10) +#define FSR_FCC1_SHIFT 11 +#define FSR_FCC1 (1 << FSR_FCC1_SHIFT) +#define FSR_FCC0_SHIFT 10 +#define FSR_FCC0 (1 << FSR_FCC0_SHIFT) /* MMU */ #define MMU_E (1<<0) Modified: trunk/target-sparc/translate.c =================================================================== --- trunk/target-sparc/translate.c 2008-04-22 21:57:57 UTC (rev 4242) +++ trunk/target-sparc/translate.c 2008-04-23 17:12:35 UTC (rev 4243) @@ -266,28 +266,28 @@ static inline void gen_mov_reg_N(TCGv reg, TCGv src) { tcg_gen_extu_i32_tl(reg, src); - tcg_gen_shri_tl(reg, reg, 23); + tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT); tcg_gen_andi_tl(reg, reg, 0x1); } static inline void gen_mov_reg_Z(TCGv reg, TCGv src) { tcg_gen_extu_i32_tl(reg, src); - tcg_gen_shri_tl(reg, reg, 22); + tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT); tcg_gen_andi_tl(reg, reg, 0x1); } static inline void gen_mov_reg_V(TCGv reg, TCGv src) { tcg_gen_extu_i32_tl(reg, src); - tcg_gen_shri_tl(reg, reg, 21); + tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT); tcg_gen_andi_tl(reg, reg, 0x1); } static inline void gen_mov_reg_C(TCGv reg, TCGv src) { tcg_gen_extu_i32_tl(reg, src); - tcg_gen_shri_tl(reg, reg, 20); + tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT); tcg_gen_andi_tl(reg, reg, 0x1); } @@ -965,7 +965,7 @@ unsigned int fcc_offset) { tcg_gen_extu_i32_tl(reg, src); - tcg_gen_shri_tl(reg, reg, 10 + fcc_offset); + tcg_gen_shri_tl(reg, reg, FSR_FCC0_SHIFT + fcc_offset); tcg_gen_andi_tl(reg, reg, 0x1); } @@ -973,7 +973,7 @@ unsigned int fcc_offset) { tcg_gen_extu_i32_tl(reg, src); - tcg_gen_shri_tl(reg, reg, 11 + fcc_offset); + tcg_gen_shri_tl(reg, reg, FSR_FCC1_SHIFT + fcc_offset); tcg_gen_andi_tl(reg, reg, 0x1); }