[Qemu-devel] [4318] Avoid some brconds

[Qemu-devel] [4318] Avoid some brconds

[Blue Swirl]

Revision: 4318
          http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=4318
Author:   blueswir1
Date:     2008-05-04 08:06:33 +0000 (Sun, 04 May 2008)

Log Message:
-----------
Avoid some brconds

Modified Paths:
--------------
    trunk/target-sparc/translate.c

Modified: trunk/target-sparc/translate.c
===================================================================
--- trunk/target-sparc/translate.c	2008-05-04 06:38:18 UTC (rev 4317)
+++ trunk/target-sparc/translate.c	2008-05-04 08:06:33 UTC (rev 4318)
@@ -379,38 +379,32 @@
 static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2)
 {
     TCGv r_temp;
-    int l1;
 
-    l1 = gen_new_label();
-
     r_temp = tcg_temp_new(TCG_TYPE_TL);
     tcg_gen_xor_tl(r_temp, src1, src2);
     tcg_gen_xori_tl(r_temp, r_temp, -1);
     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
     tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
-    tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
-    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
-    gen_set_label(l1);
+    tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
+    tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
+    tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
 }
 
 #ifdef TARGET_SPARC64
 static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2)
 {
     TCGv r_temp;
-    int l1;
 
-    l1 = gen_new_label();
-
     r_temp = tcg_temp_new(TCG_TYPE_TL);
     tcg_gen_xor_tl(r_temp, src1, src2);
     tcg_gen_xori_tl(r_temp, r_temp, -1);
     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
     tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
-    tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
-    tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF);
-    gen_set_label(l1);
+    tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
+    tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
+    tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
 }
 #endif
 
@@ -570,36 +564,30 @@
 static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2)
 {
     TCGv r_temp;
-    int l1;
 
-    l1 = gen_new_label();
-
     r_temp = tcg_temp_new(TCG_TYPE_TL);
     tcg_gen_xor_tl(r_temp, src1, src2);
     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
     tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
-    tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
-    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
-    gen_set_label(l1);
+    tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
+    tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
+    tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
 }
 
 #ifdef TARGET_SPARC64
 static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2)
 {
     TCGv r_temp;
-    int l1;
 
-    l1 = gen_new_label();
-
     r_temp = tcg_temp_new(TCG_TYPE_TL);
     tcg_gen_xor_tl(r_temp, src1, src2);
     tcg_gen_xor_tl(cpu_tmp0, src1, dst);
     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
     tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
-    tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
-    tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF);
-    gen_set_label(l1);
+    tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
+    tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
+    tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
 }
 #endif