From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Jtljf-0002BJ-DI for qemu-devel@nongnu.org; Wed, 07 May 2008 11:39:15 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Jtlje-0002B2-7B for qemu-devel@nongnu.org; Wed, 07 May 2008 11:39:14 -0400 Received: from [199.232.76.173] (port=47693 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Jtlje-0002Ar-2E for qemu-devel@nongnu.org; Wed, 07 May 2008 11:39:14 -0400 Received: from savannah.gnu.org ([199.232.41.3] helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1Jtljd-0000tc-OD for qemu-devel@nongnu.org; Wed, 07 May 2008 11:39:13 -0400 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.63) (envelope-from ) id 1Jtljd-0004HX-0S for qemu-devel@nongnu.org; Wed, 07 May 2008 15:39:13 +0000 Received: from ths by cvs.savannah.gnu.org with local (Exim 4.63) (envelope-from ) id 1Jtljc-0004HT-Qg for qemu-devel@nongnu.org; Wed, 07 May 2008 15:39:12 +0000 MIME-Version: 1.0 Errors-To: ths Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Thiemo Seufer Message-Id: Date: Wed, 07 May 2008 15:39:12 +0000 Subject: [Qemu-devel] [4381] Mention missing CPU save/restore. Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 4381 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=4381 Author: ths Date: 2008-05-07 15:39:12 +0000 (Wed, 07 May 2008) Log Message: ----------- Mention missing CPU save/restore. Modified Paths: -------------- trunk/target-mips/TODO Modified: trunk/target-mips/TODO =================================================================== --- trunk/target-mips/TODO 2008-05-07 15:33:57 UTC (rev 4380) +++ trunk/target-mips/TODO 2008-05-07 15:39:12 UTC (rev 4381) @@ -29,6 +29,7 @@ To cope with these differences, Qemu currently flushes the TLB at each ASID change. Using the MMU modes to implement ASIDs hinges on implementing the global bit efficiently. +- save/restore of the CPU state is not implemented (see machine.c). MIPS64 ------