From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1JxIwh-0005ch-Ki for qemu-devel@nongnu.org; Sat, 17 May 2008 05:43:19 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1JxIwg-0005bp-IT for qemu-devel@nongnu.org; Sat, 17 May 2008 05:43:19 -0400 Received: from [199.232.76.173] (port=45003 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1JxIwg-0005bc-8S for qemu-devel@nongnu.org; Sat, 17 May 2008 05:43:18 -0400 Received: from savannah.gnu.org ([199.232.41.3]:33439 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1JxIwf-0007ra-UO for qemu-devel@nongnu.org; Sat, 17 May 2008 05:43:18 -0400 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.63) (envelope-from ) id 1JxIwe-0001z7-6L for qemu-devel@nongnu.org; Sat, 17 May 2008 09:43:16 +0000 Received: from blueswir1 by cvs.savannah.gnu.org with local (Exim 4.63) (envelope-from ) id 1JxIwb-0001yg-Rh for qemu-devel@nongnu.org; Sat, 17 May 2008 09:43:14 +0000 MIME-Version: 1.0 Errors-To: blueswir1 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Blue Swirl Message-Id: Date: Sat, 17 May 2008 09:43:14 +0000 Subject: [Qemu-devel] [4467] Generate better code for Sparc32 shifts Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 4467 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=4467 Author: blueswir1 Date: 2008-05-17 09:43:12 +0000 (Sat, 17 May 2008) Log Message: ----------- Generate better code for Sparc32 shifts Modified Paths: -------------- trunk/target-sparc/translate.c Modified: trunk/target-sparc/translate.c =================================================================== --- trunk/target-sparc/translate.c 2008-05-17 09:41:14 UTC (rev 4466) +++ trunk/target-sparc/translate.c 2008-05-17 09:43:12 UTC (rev 4467) @@ -3008,18 +3008,33 @@ break; #ifndef TARGET_SPARC64 case 0x25: /* sll */ - tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f); - tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0); + if (IS_IMM) { /* immediate */ + rs2 = GET_FIELDs(insn, 20, 31); + tcg_gen_shli_tl(cpu_dst, cpu_src1, rs2 & 0x1f); + } else { /* register */ + tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f); + tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0); + } gen_movl_TN_reg(rd, cpu_dst); break; case 0x26: /* srl */ - tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f); - tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0); + if (IS_IMM) { /* immediate */ + rs2 = GET_FIELDs(insn, 20, 31); + tcg_gen_shri_tl(cpu_dst, cpu_src1, rs2 & 0x1f); + } else { /* register */ + tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f); + tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0); + } gen_movl_TN_reg(rd, cpu_dst); break; case 0x27: /* sra */ - tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f); - tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0); + if (IS_IMM) { /* immediate */ + rs2 = GET_FIELDs(insn, 20, 31); + tcg_gen_sari_tl(cpu_dst, cpu_src1, rs2 & 0x1f); + } else { /* register */ + tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f); + tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0); + } gen_movl_TN_reg(rd, cpu_dst); break; #endif