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From: Thiemo Seufer <ths@networkno.de>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [4650] Proper sign extensions for 32-bit divisions, spotted by Richard Sandiford.
Date: Mon, 02 Jun 2008 07:15:20 +0000	[thread overview]
Message-ID: <E1K34GG-0008R6-JC@cvs.savannah.gnu.org> (raw)

Revision: 4650
          http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=4650
Author:   ths
Date:     2008-06-02 07:15:18 +0000 (Mon, 02 Jun 2008)

Log Message:
-----------
Proper sign extensions for 32-bit divisions, spotted by Richard Sandiford.

Modified Paths:
--------------
    trunk/target-mips/translate.c

Modified: trunk/target-mips/translate.c
===================================================================
--- trunk/target-mips/translate.c	2008-06-02 03:12:06 UTC (rev 4649)
+++ trunk/target-mips/translate.c	2008-06-02 07:15:18 UTC (rev 4650)
@@ -1900,6 +1900,8 @@
         {
             int l1 = gen_new_label();
 
+            tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
+            tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
             tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, l1);
             {
                 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
@@ -1912,6 +1914,8 @@
                 tcg_gen_rem_i64(r_tmp2, r_tmp1, r_tmp2);
                 tcg_gen_trunc_i64_tl(cpu_T[0], r_tmp3);
                 tcg_gen_trunc_i64_tl(cpu_T[1], r_tmp2);
+                tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
+                tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
                 gen_store_LO(cpu_T[0], 0);
                 gen_store_HI(cpu_T[1], 0);
             }
@@ -1923,6 +1927,7 @@
         {
             int l1 = gen_new_label();
 
+            tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
             tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, l1);
             {
                 TCGv r_tmp1 = new_tmp();
@@ -1962,8 +1967,8 @@
             {
                 int l2 = gen_new_label();
 
-                tcg_gen_brcondi_tl(TCG_COND_NE, cpu_T[0], 1ULL << 63, l2);
-                tcg_gen_brcondi_tl(TCG_COND_NE, cpu_T[1], -1ULL, l2);
+                tcg_gen_brcondi_tl(TCG_COND_NE, cpu_T[0], -1LL << 63, l2);
+                tcg_gen_brcondi_tl(TCG_COND_NE, cpu_T[1], -1LL, l2);
                 {
                     tcg_gen_movi_tl(cpu_T[1], 0);
                     gen_store_LO(cpu_T[0], 0);

                 reply	other threads:[~2008-06-02  7:15 UTC|newest]

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