From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1K3wxU-0003Z4-Iy for qemu-devel@nongnu.org; Wed, 04 Jun 2008 13:39:36 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1K3wxT-0003Yc-Vf for qemu-devel@nongnu.org; Wed, 04 Jun 2008 13:39:36 -0400 Received: from [199.232.76.173] (port=50641 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1K3wxT-0003YQ-KT for qemu-devel@nongnu.org; Wed, 04 Jun 2008 13:39:35 -0400 Received: from savannah.gnu.org ([199.232.41.3]:55148 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1K3wxT-0006jh-6N for qemu-devel@nongnu.org; Wed, 04 Jun 2008 13:39:35 -0400 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.63) (envelope-from ) id 1K3wxR-0007v5-VQ for qemu-devel@nongnu.org; Wed, 04 Jun 2008 17:39:34 +0000 Received: from bellard by cvs.savannah.gnu.org with local (Exim 4.63) (envelope-from ) id 1K3wxR-0007v0-LO for qemu-devel@nongnu.org; Wed, 04 Jun 2008 17:39:33 +0000 MIME-Version: 1.0 Errors-To: bellard Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Fabrice Bellard Message-Id: Date: Wed, 04 Jun 2008 17:39:33 +0000 Subject: [Qemu-devel] [4668] SVM: added tsc_offset Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 4668 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=4668 Author: bellard Date: 2008-06-04 17:39:33 +0000 (Wed, 04 Jun 2008) Log Message: ----------- SVM: added tsc_offset Modified Paths: -------------- trunk/target-i386/cpu.h trunk/target-i386/op_helper.c Modified: trunk/target-i386/cpu.h =================================================================== --- trunk/target-i386/cpu.h 2008-06-04 17:37:03 UTC (rev 4667) +++ trunk/target-i386/cpu.h 2008-06-04 17:39:33 UTC (rev 4668) @@ -119,9 +119,9 @@ #define ID_MASK 0x00200000 /* hidden flags - used internally by qemu to represent additional cpu - states. Only the CPL and INHIBIT_IRQ are not redundant. We avoid - using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring - with eflags. */ + states. Only the CPL, INHIBIT_IRQ, SMM and SVMI are not + redundant. We avoid using the IOPL_MASK, TF_MASK and VM_MASK bit + position to ease oring with eflags. */ /* current cpl */ #define HF_CPL_SHIFT 0 /* true if soft mmu is being used */ @@ -543,6 +543,7 @@ target_phys_addr_t vm_hsave; target_phys_addr_t vm_vmcb; + uint64_t tsc_offset; uint64_t intercept; uint16_t intercept_cr_read; uint16_t intercept_cr_write; Modified: trunk/target-i386/op_helper.c =================================================================== --- trunk/target-i386/op_helper.c 2008-06-04 17:37:03 UTC (rev 4667) +++ trunk/target-i386/op_helper.c 2008-06-04 17:39:33 UTC (rev 4668) @@ -3005,7 +3005,7 @@ } helper_svm_check_intercept_param(SVM_EXIT_RDTSC, 0); - val = cpu_get_tsc(env); + val = cpu_get_tsc(env) + env->tsc_offset; EAX = (uint32_t)(val); EDX = (uint32_t)(val >> 32); } @@ -4851,6 +4851,8 @@ /* enable intercepts */ env->hflags |= HF_SVMI_MASK; + env->tsc_offset = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, control.tsc_offset)); + env->gdt.base = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.gdtr.base)); env->gdt.limit = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, save.gdtr.limit)); @@ -5226,6 +5228,7 @@ env->intercept = 0; env->intercept_exceptions = 0; env->interrupt_request &= ~CPU_INTERRUPT_VIRQ; + env->tsc_offset = 0; env->gdt.base = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.gdtr.base)); env->gdt.limit = ldl_phys(env->vm_hsave + offsetof(struct vmcb, save.gdtr.limit));