From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1K6Nk8-0005ky-8E for qemu-devel@nongnu.org; Wed, 11 Jun 2008 06:39:52 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1K6Nk7-0005kX-Qj for qemu-devel@nongnu.org; Wed, 11 Jun 2008 06:39:51 -0400 Received: from [199.232.76.173] (port=40632 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1K6Nk7-0005kE-I8 for qemu-devel@nongnu.org; Wed, 11 Jun 2008 06:39:51 -0400 Received: from savannah.gnu.org ([199.232.41.3]:56494 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1K6Nk7-0006r3-Cl for qemu-devel@nongnu.org; Wed, 11 Jun 2008 06:39:51 -0400 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.63) (envelope-from ) id 1K6Nk5-00043N-FT for qemu-devel@nongnu.org; Wed, 11 Jun 2008 10:39:49 +0000 Received: from ths by cvs.savannah.gnu.org with local (Exim 4.63) (envelope-from ) id 1K6Nk5-00043J-4w for qemu-devel@nongnu.org; Wed, 11 Jun 2008 10:39:49 +0000 MIME-Version: 1.0 Errors-To: ths Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Thiemo Seufer Message-Id: Date: Wed, 11 Jun 2008 10:39:49 +0000 Subject: [Qemu-devel] [4728] Move FP TNs to cpu env. Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 4728 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=4728 Author: ths Date: 2008-06-11 10:39:48 +0000 (Wed, 11 Jun 2008) Log Message: ----------- Move FP TNs to cpu env. Modified Paths: -------------- trunk/target-mips/cpu.h trunk/target-mips/exec.h trunk/target-mips/translate.c Modified: trunk/target-mips/cpu.h =================================================================== --- trunk/target-mips/cpu.h 2008-06-11 09:44:44 UTC (rev 4727) +++ trunk/target-mips/cpu.h 2008-06-11 10:39:48 UTC (rev 4728) @@ -70,11 +70,6 @@ struct CPUMIPSFPUContext { /* Floating point registers */ fpr_t fpr[32]; -#ifndef USE_HOST_FLOAT_REGS - fpr_t ft0; - fpr_t ft1; - fpr_t ft2; -#endif float_status fp_status; /* fpu implementation/revision register (fir) */ uint32_t fcr0; @@ -149,6 +144,12 @@ target_ulong t0; target_ulong t1; #endif + /* temporary hack for FP globals */ +#ifndef USE_HOST_FLOAT_REGS + fpr_t ft0; + fpr_t ft1; + fpr_t ft2; +#endif target_ulong HI[MIPS_TC_MAX][MIPS_DSP_ACC]; target_ulong LO[MIPS_TC_MAX][MIPS_DSP_ACC]; target_ulong ACX[MIPS_TC_MAX][MIPS_DSP_ACC]; Modified: trunk/target-mips/exec.h =================================================================== --- trunk/target-mips/exec.h 2008-06-11 09:44:44 UTC (rev 4727) +++ trunk/target-mips/exec.h 2008-06-11 10:39:48 UTC (rev 4728) @@ -21,24 +21,24 @@ #if defined (USE_HOST_FLOAT_REGS) #error "implement me." #else -#define FDT0 (env->fpu->ft0.fd) -#define FDT1 (env->fpu->ft1.fd) -#define FDT2 (env->fpu->ft2.fd) -#define FST0 (env->fpu->ft0.fs[FP_ENDIAN_IDX]) -#define FST1 (env->fpu->ft1.fs[FP_ENDIAN_IDX]) -#define FST2 (env->fpu->ft2.fs[FP_ENDIAN_IDX]) -#define FSTH0 (env->fpu->ft0.fs[!FP_ENDIAN_IDX]) -#define FSTH1 (env->fpu->ft1.fs[!FP_ENDIAN_IDX]) -#define FSTH2 (env->fpu->ft2.fs[!FP_ENDIAN_IDX]) -#define DT0 (env->fpu->ft0.d) -#define DT1 (env->fpu->ft1.d) -#define DT2 (env->fpu->ft2.d) -#define WT0 (env->fpu->ft0.w[FP_ENDIAN_IDX]) -#define WT1 (env->fpu->ft1.w[FP_ENDIAN_IDX]) -#define WT2 (env->fpu->ft2.w[FP_ENDIAN_IDX]) -#define WTH0 (env->fpu->ft0.w[!FP_ENDIAN_IDX]) -#define WTH1 (env->fpu->ft1.w[!FP_ENDIAN_IDX]) -#define WTH2 (env->fpu->ft2.w[!FP_ENDIAN_IDX]) +#define FDT0 (env->ft0.fd) +#define FDT1 (env->ft1.fd) +#define FDT2 (env->ft2.fd) +#define FST0 (env->ft0.fs[FP_ENDIAN_IDX]) +#define FST1 (env->ft1.fs[FP_ENDIAN_IDX]) +#define FST2 (env->ft2.fs[FP_ENDIAN_IDX]) +#define FSTH0 (env->ft0.fs[!FP_ENDIAN_IDX]) +#define FSTH1 (env->ft1.fs[!FP_ENDIAN_IDX]) +#define FSTH2 (env->ft2.fs[!FP_ENDIAN_IDX]) +#define DT0 (env->ft0.d) +#define DT1 (env->ft1.d) +#define DT2 (env->ft2.d) +#define WT0 (env->ft0.w[FP_ENDIAN_IDX]) +#define WT1 (env->ft1.w[FP_ENDIAN_IDX]) +#define WT2 (env->ft2.w[FP_ENDIAN_IDX]) +#define WTH0 (env->ft0.w[!FP_ENDIAN_IDX]) +#define WTH1 (env->ft1.w[!FP_ENDIAN_IDX]) +#define WTH2 (env->ft2.w[!FP_ENDIAN_IDX]) #endif #include "cpu.h" Modified: trunk/target-mips/translate.c =================================================================== --- trunk/target-mips/translate.c 2008-06-11 09:44:44 UTC (rev 4727) +++ trunk/target-mips/translate.c 2008-06-11 10:39:48 UTC (rev 4728) @@ -7386,9 +7386,9 @@ fpu_fprintf(f, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%08x(0x%02x)\n", env->fpu->fcr0, env->fpu->fcr31, is_fpu64, env->fpu->fp_status, get_float_exception_flags(&env->fpu->fp_status)); - fpu_fprintf(f, "FT0: "); printfpr(&env->fpu->ft0); - fpu_fprintf(f, "FT1: "); printfpr(&env->fpu->ft1); - fpu_fprintf(f, "FT2: "); printfpr(&env->fpu->ft2); + fpu_fprintf(f, "FT0: "); printfpr(&env->ft0); + fpu_fprintf(f, "FT1: "); printfpr(&env->ft1); + fpu_fprintf(f, "FT2: "); printfpr(&env->ft2); for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) { fpu_fprintf(f, "%3s: ", fregnames[i]); printfpr(&env->fpu->fpr[i]);