From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1K6dJH-0003v6-Sb for qemu-devel@nongnu.org; Wed, 11 Jun 2008 23:17:12 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1K6dJH-0003uT-0U for qemu-devel@nongnu.org; Wed, 11 Jun 2008 23:17:11 -0400 Received: from [199.232.76.173] (port=44720 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1K6dJG-0003uN-SO for qemu-devel@nongnu.org; Wed, 11 Jun 2008 23:17:10 -0400 Received: from savannah.gnu.org ([199.232.41.3]:37202 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1K6dJG-00072u-R3 for qemu-devel@nongnu.org; Wed, 11 Jun 2008 23:17:10 -0400 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.63) (envelope-from ) id 1K6dJE-0006NY-Pz for qemu-devel@nongnu.org; Thu, 12 Jun 2008 03:17:09 +0000 Received: from ths by cvs.savannah.gnu.org with local (Exim 4.63) (envelope-from ) id 1K6dJD-0006NS-TB for qemu-devel@nongnu.org; Thu, 12 Jun 2008 03:17:08 +0000 MIME-Version: 1.0 Errors-To: ths Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Thiemo Seufer Message-Id: Date: Thu, 12 Jun 2008 03:17:07 +0000 Subject: [Qemu-devel] [4737] TCGify the simplest FP instructions. Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 4737 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=4737 Author: ths Date: 2008-06-12 03:17:06 +0000 (Thu, 12 Jun 2008) Log Message: ----------- TCGify the simplest FP instructions. Modified Paths: -------------- trunk/target-mips/op.c trunk/target-mips/op_mem.c trunk/target-mips/translate.c Modified: trunk/target-mips/op.c =================================================================== --- trunk/target-mips/op.c 2008-06-12 03:15:13 UTC (rev 4736) +++ trunk/target-mips/op.c 2008-06-12 03:17:06 UTC (rev 4737) @@ -377,14 +377,6 @@ #define FLOAT_OP(name, p) void OPPROTO op_float_##name##_##p(void) -FLOAT_OP(cvtps, s) -{ - WT2 = WT0; - WTH2 = WT1; - DEBUG_FPU_STATE(); - FORCE_RET(); -} - FLOAT_OP(pll, ps) { DT2 = ((uint64_t)WT0 << 32) | WT1; @@ -609,25 +601,6 @@ FLOAT_UNOP(chs) #undef FLOAT_UNOP -FLOAT_OP(mov, d) -{ - FDT2 = FDT0; - DEBUG_FPU_STATE(); - FORCE_RET(); -} -FLOAT_OP(mov, s) -{ - FST2 = FST0; - DEBUG_FPU_STATE(); - FORCE_RET(); -} -FLOAT_OP(mov, ps) -{ - FST2 = FST0; - FSTH2 = FSTH0; - DEBUG_FPU_STATE(); - FORCE_RET(); -} FLOAT_OP(alnv, ps) { switch (T0 & 0x7) { Modified: trunk/target-mips/op_mem.c =================================================================== --- trunk/target-mips/op_mem.c 2008-06-12 03:15:13 UTC (rev 4736) +++ trunk/target-mips/op_mem.c 2008-06-12 03:17:06 UTC (rev 4737) @@ -267,14 +267,3 @@ FORCE_RET(); } #endif /* TARGET_MIPS64 */ - -void glue(op_luxc1, MEMSUFFIX) (void) -{ - DT0 = glue(ldq, MEMSUFFIX)(T0 & ~0x7); - FORCE_RET(); -} -void glue(op_suxc1, MEMSUFFIX) (void) -{ - glue(stq, MEMSUFFIX)(T0 & ~0x7, DT0); - FORCE_RET(); -} Modified: trunk/target-mips/translate.c =================================================================== --- trunk/target-mips/translate.c 2008-06-12 03:15:13 UTC (rev 4736) +++ trunk/target-mips/translate.c 2008-06-12 03:17:06 UTC (rev 4737) @@ -960,8 +960,6 @@ OP_LD_TABLE(wr); OP_ST_TABLE(wl); OP_ST_TABLE(wr); -OP_LD_TABLE(uxc1); -OP_ST_TABLE(uxc1); #define OP_LD(insn,fname) \ void inline op_ldst_##insn(DisasContext *ctx) \ @@ -5651,8 +5649,7 @@ break; case FOP(6, 16): gen_load_fpr32(fpu32_T[0], fs); - gen_op_float_mov_s(); - gen_store_fpr32(fpu32_T[2], fd); + gen_store_fpr32(fpu32_T[0], fd); opn = "mov.s"; break; case FOP(7, 16): @@ -5803,9 +5800,12 @@ break; case FOP(38, 16): check_cp1_64bitmode(ctx); - gen_load_fpr32(fpu32_T[1], fs); - gen_load_fpr32(fpu32_T[0], ft); - gen_op_float_cvtps_s(); + gen_load_fpr32(fpu32_T[0], fs); + gen_load_fpr32(fpu32_T[1], ft); + tcg_gen_extu_i32_i64(fpu64_T[0], fpu32_T[0]); + tcg_gen_extu_i32_i64(fpu64_T[1], fpu32_T[1]); + tcg_gen_shli_i64(fpu64_T[1], fpu64_T[1], 32); + tcg_gen_or_i64(fpu64_T[2], fpu64_T[0], fpu64_T[1]); gen_store_fpr64(ctx, fpu64_T[2], fd); opn = "cvt.ps.s"; break; @@ -5889,8 +5889,7 @@ case FOP(6, 17): check_cp1_registers(ctx, fs | fd); gen_load_fpr64(ctx, fpu64_T[0], fs); - gen_op_float_mov_d(); - gen_store_fpr64(ctx, fpu64_T[2], fd); + gen_store_fpr64(ctx, fpu64_T[0], fd); opn = "mov.d"; break; case FOP(7, 17): @@ -6156,9 +6155,8 @@ check_cp1_64bitmode(ctx); gen_load_fpr32(fpu32_T[0], fs); gen_load_fpr32h(fpu32h_T[0], fs); - gen_op_float_mov_ps(); - gen_store_fpr32(fpu32_T[2], fd); - gen_store_fpr32h(fpu32h_T[2], fd); + gen_store_fpr32(fpu32_T[0], fd); + gen_store_fpr32h(fpu32h_T[0], fd); opn = "mov.ps"; break; case FOP(7, 22): @@ -6407,7 +6405,8 @@ break; case OPC_LUXC1: check_cp1_64bitmode(ctx); - op_ldst(luxc1); + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ~0x7); + tcg_gen_qemu_ld64(fpu64_T[0], cpu_T[0], ctx->mem_idx); gen_store_fpr64(ctx, fpu64_T[0], fd); opn = "luxc1"; break; @@ -6429,7 +6428,8 @@ case OPC_SUXC1: check_cp1_64bitmode(ctx); gen_load_fpr64(ctx, fpu64_T[0], fs); - op_ldst(suxc1); + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ~0x7); + tcg_gen_qemu_st64(fpu64_T[0], cpu_T[0], ctx->mem_idx); opn = "suxc1"; store = 1; break;