From: malc <av1474@comtv.ru>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [4778] Shuffle contents of tcg_target_reg_alloc_order
Date: Mon, 23 Jun 2008 05:47:04 +0000 [thread overview]
Message-ID: <E1KAetM-00083D-3e@cvs.savannah.gnu.org> (raw)
Revision: 4778
http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=4778
Author: malc
Date: 2008-06-23 05:47:03 +0000 (Mon, 23 Jun 2008)
Log Message:
-----------
Shuffle contents of tcg_target_reg_alloc_order
Move reserved/volatile registers down. Currently qemu_ld/stXX are
marked with TCG_OPF_CALL_CLOBBER and since memory accesses are
frequent and R3 through R12 are volatile moving this down results in
less spills and tighter generated code.
Modified Paths:
--------------
trunk/tcg/ppc/tcg-target.c
Modified: trunk/tcg/ppc/tcg-target.c
===================================================================
--- trunk/tcg/ppc/tcg-target.c 2008-06-22 14:10:45 UTC (rev 4777)
+++ trunk/tcg/ppc/tcg-target.c 2008-06-23 05:47:03 UTC (rev 4778)
@@ -67,9 +67,20 @@
};
static const int tcg_target_reg_alloc_order[] = {
- TCG_REG_R0,
- TCG_REG_R1,
- TCG_REG_R2,
+ TCG_REG_R14,
+ TCG_REG_R15,
+ TCG_REG_R16,
+ TCG_REG_R17,
+ TCG_REG_R18,
+ TCG_REG_R19,
+ TCG_REG_R20,
+ TCG_REG_R21,
+ TCG_REG_R22,
+ TCG_REG_R23,
+ TCG_REG_R28,
+ TCG_REG_R29,
+ TCG_REG_R30,
+ TCG_REG_R31,
TCG_REG_R3,
TCG_REG_R4,
TCG_REG_R5,
@@ -81,24 +92,13 @@
TCG_REG_R11,
TCG_REG_R12,
TCG_REG_R13,
- TCG_REG_R14,
- TCG_REG_R15,
- TCG_REG_R16,
- TCG_REG_R17,
- TCG_REG_R18,
- TCG_REG_R19,
- TCG_REG_R20,
- TCG_REG_R21,
- TCG_REG_R22,
- TCG_REG_R23,
+ TCG_REG_R0,
+ TCG_REG_R1,
+ TCG_REG_R2,
TCG_REG_R24,
TCG_REG_R25,
TCG_REG_R26,
- TCG_REG_R27,
- TCG_REG_R28,
- TCG_REG_R29,
- TCG_REG_R30,
- TCG_REG_R31
+ TCG_REG_R27
};
static const int tcg_target_call_iarg_regs[] = {
reply other threads:[~2008-06-23 5:47 UTC|newest]
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