From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KDm2a-00008F-6p for qemu-devel@nongnu.org; Tue, 01 Jul 2008 16:01:28 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KDm2Z-00007s-JG for qemu-devel@nongnu.org; Tue, 01 Jul 2008 16:01:27 -0400 Received: from [199.232.76.173] (port=57542 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KDm2Z-00007p-Gq for qemu-devel@nongnu.org; Tue, 01 Jul 2008 16:01:27 -0400 Received: from savannah.gnu.org ([199.232.41.3]:43661 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1KDm2Z-0003d6-NW for qemu-devel@nongnu.org; Tue, 01 Jul 2008 16:01:27 -0400 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.63) (envelope-from ) id 1KDm2T-0003UY-Rg for qemu-devel@nongnu.org; Tue, 01 Jul 2008 20:01:21 +0000 Received: from pbrook by cvs.savannah.gnu.org with local (Exim 4.63) (envelope-from ) id 1KDm2T-0003Tu-6l for qemu-devel@nongnu.org; Tue, 01 Jul 2008 20:01:21 +0000 MIME-Version: 1.0 Errors-To: pbrook Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Paul Brook Message-Id: Date: Tue, 01 Jul 2008 20:01:21 +0000 Subject: [Qemu-devel] [4817] Move interrupt_request and user_mode_only to common cpu state. Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 4817 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=4817 Author: pbrook Date: 2008-07-01 20:01:19 +0000 (Tue, 01 Jul 2008) Log Message: ----------- Move interrupt_request and user_mode_only to common cpu state. Save and restore env->interrupt_request and env->halted. Modified Paths: -------------- trunk/cpu-defs.h trunk/exec.c trunk/target-alpha/cpu.h trunk/target-arm/cpu.h trunk/target-cris/cpu.h trunk/target-i386/cpu.h trunk/target-i386/machine.c trunk/target-m68k/cpu.h trunk/target-mips/cpu.h trunk/target-ppc/cpu.h trunk/target-sh4/cpu.h trunk/target-sparc/cpu.h Modified: trunk/cpu-defs.h =================================================================== --- trunk/cpu-defs.h 2008-07-01 19:28:23 UTC (rev 4816) +++ trunk/cpu-defs.h 2008-07-01 20:01:19 UTC (rev 4817) @@ -153,7 +153,8 @@ accessed */ \ target_ulong mem_io_vaddr; /* target virtual addr at which the \ memory was accessed */ \ - int halted; /* TRUE if the CPU is in suspend state */ \ + uint32_t halted; /* Nonzero if the CPU is in suspend state */ \ + uint32_t interrupt_request; \ /* The meaning of the MMU modes is defined in the target code. */ \ CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ @@ -188,6 +189,8 @@ jmp_buf jmp_env; \ int exception_index; \ \ + int user_mode_only; \ + \ void *next_cpu; /* next CPU sharing TB cache */ \ int cpu_index; /* CPU index (informative) */ \ int running; /* Nonzero if cpu is currently running(usermode). */ \ Modified: trunk/exec.c =================================================================== --- trunk/exec.c 2008-07-01 19:28:23 UTC (rev 4816) +++ trunk/exec.c 2008-07-01 20:01:19 UTC (rev 4817) @@ -443,6 +443,33 @@ #endif } +#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) + +#define CPU_COMMON_SAVE_VERSION 1 + +static void cpu_common_save(QEMUFile *f, void *opaque) +{ + CPUState *env = opaque; + + qemu_put_be32s(f, &env->halted); + qemu_put_be32s(f, &env->interrupt_request); +} + +static int cpu_common_load(QEMUFile *f, void *opaque, int version_id) +{ + CPUState *env = opaque; + + if (version_id != CPU_COMMON_SAVE_VERSION) + return -EINVAL; + + qemu_get_be32s(f, &env->halted); + qemu_put_be32s(f, &env->interrupt_request); + tlb_flush(env, 1); + + return 0; +} +#endif + void cpu_exec_init(CPUState *env) { CPUState **penv; @@ -459,6 +486,8 @@ env->nb_watchpoints = 0; *penv = env; #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) + register_savevm("cpu_common", cpu_index, CPU_COMMON_SAVE_VERSION, + cpu_common_save, cpu_common_load, env); register_savevm("cpu", cpu_index, CPU_SAVE_VERSION, cpu_save, cpu_load, env); #endif Modified: trunk/target-alpha/cpu.h =================================================================== --- trunk/target-alpha/cpu.h 2008-07-01 19:28:23 UTC (rev 4816) +++ trunk/target-alpha/cpu.h 2008-07-01 20:01:19 UTC (rev 4817) @@ -282,11 +282,9 @@ /* Those resources are used only in Qemu core */ CPU_COMMON - int user_mode_only; /* user mode only simulation */ uint32_t hflags; int error_code; - int interrupt_request; uint32_t features; uint32_t amask; Modified: trunk/target-arm/cpu.h =================================================================== --- trunk/target-arm/cpu.h 2008-07-01 19:28:23 UTC (rev 4816) +++ trunk/target-arm/cpu.h 2008-07-01 20:01:19 UTC (rev 4817) @@ -156,10 +156,6 @@ int (*get_irq_vector)(struct CPUARMState *); void *irq_opaque; - /* exception/interrupt handling */ - int interrupt_request; - int user_mode_only; - /* VFP coprocessor state. */ struct { float64 regs[32]; Modified: trunk/target-cris/cpu.h =================================================================== --- trunk/target-cris/cpu.h 2008-07-01 19:28:23 UTC (rev 4816) +++ trunk/target-cris/cpu.h 2008-07-01 20:01:19 UTC (rev 4817) @@ -125,7 +125,6 @@ /* X flag at the time of cc snapshot. */ int cc_x; - int interrupt_request; int interrupt_vector; int fault_vector; int trap_vector; @@ -156,8 +155,6 @@ uint32_t lo; } tlbsets[2][4][16]; - int user_mode_only; - CPU_COMMON } CPUCRISState; Modified: trunk/target-i386/cpu.h =================================================================== --- trunk/target-i386/cpu.h 2008-07-01 19:28:23 UTC (rev 4816) +++ trunk/target-i386/cpu.h 2008-07-01 20:01:19 UTC (rev 4817) @@ -567,8 +567,6 @@ target_ulong exception_next_eip; target_ulong dr[8]; /* debug registers */ uint32_t smbase; - int interrupt_request; - int user_mode_only; /* user mode only simulation */ int old_exception; /* exception in flight */ CPU_COMMON @@ -726,7 +724,7 @@ #define cpu_signal_handler cpu_x86_signal_handler #define cpu_list x86_cpu_list -#define CPU_SAVE_VERSION 5 +#define CPU_SAVE_VERSION 6 /* MMU modes definitions */ #define MMU_MODE0_SUFFIX _kernel Modified: trunk/target-i386/machine.c =================================================================== --- trunk/target-i386/machine.c 2008-07-01 19:28:23 UTC (rev 4816) +++ trunk/target-i386/machine.c 2008-07-01 20:01:19 UTC (rev 4817) @@ -123,7 +123,6 @@ qemu_put_be64s(f, &env->pat); qemu_put_be32s(f, &env->hflags2); - qemu_put_be32s(f, (uint32_t *)&env->halted); qemu_put_be64s(f, &env->vm_hsave); qemu_put_be64s(f, &env->vm_vmcb); @@ -169,7 +168,8 @@ uint16_t fpus, fpuc, fptag, fpregs_format; int32_t a20_mask; - if (version_id != 3 && version_id != 4 && version_id != 5) + if (version_id != 3 && version_id != 4 && version_id != 5 + && version_id != 6) return -EINVAL; for(i = 0; i < CPU_NB_REGS; i++) qemu_get_betls(f, &env->regs[i]); @@ -279,7 +279,8 @@ if (version_id >= 5) { qemu_get_be64s(f, &env->pat); qemu_get_be32s(f, &env->hflags2); - qemu_get_be32s(f, (uint32_t *)&env->halted); + if (version_id < 6) + qemu_get_be32s(f, &env->halted); qemu_get_be64s(f, &env->vm_hsave); qemu_get_be64s(f, &env->vm_vmcb); Modified: trunk/target-m68k/cpu.h =================================================================== --- trunk/target-m68k/cpu.h 2008-07-01 19:28:23 UTC (rev 4816) +++ trunk/target-m68k/cpu.h 2008-07-01 20:01:19 UTC (rev 4817) @@ -103,10 +103,6 @@ /* ??? remove this. */ uint32_t t1; - /* exception/interrupt handling */ - int interrupt_request; - int user_mode_only; - int pending_vector; int pending_level; Modified: trunk/target-mips/cpu.h =================================================================== --- trunk/target-mips/cpu.h 2008-07-01 19:28:23 UTC (rev 4816) +++ trunk/target-mips/cpu.h 2008-07-01 20:01:19 UTC (rev 4817) @@ -411,9 +411,7 @@ /* We waste some space so we can handle shadow registers like TCs. */ TCState tcs[MIPS_SHADOW_SET_MAX]; /* Qemu */ - int interrupt_request; int error_code; - int user_mode_only; /* user mode only simulation */ uint32_t hflags; /* CPU State */ /* TMASK defines different execution modes */ #define MIPS_HFLAG_TMASK 0x01FF Modified: trunk/target-ppc/cpu.h =================================================================== --- trunk/target-ppc/cpu.h 2008-07-01 19:28:23 UTC (rev 4816) +++ trunk/target-ppc/cpu.h 2008-07-01 20:01:19 UTC (rev 4817) @@ -647,7 +647,6 @@ uint32_t flags; int error_code; - int interrupt_request; uint32_t pending_interrupts; #if !defined(CONFIG_USER_ONLY) /* This is the IRQ controller, which is implementation dependant @@ -671,7 +670,6 @@ opc_handler_t *opcodes[0x40]; /* Those resources are used only in Qemu core */ - int user_mode_only; /* user mode only simulation */ target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */ target_ulong hflags_nmsr; /* specific hflags, not comming from MSR */ int mmu_idx; /* precomputed MMU index to speed up mem accesses */ Modified: trunk/target-sh4/cpu.h =================================================================== --- trunk/target-sh4/cpu.h 2008-07-01 19:28:23 UTC (rev 4816) +++ trunk/target-sh4/cpu.h 2008-07-01 20:01:19 UTC (rev 4817) @@ -114,8 +114,6 @@ uint32_t expevt; /* exception event register */ uint32_t intevt; /* interrupt event register */ - int user_mode_only; - int interrupt_request; CPU_COMMON tlb_t utlb[UTLB_SIZE]; /* unified translation table */ tlb_t itlb[ITLB_SIZE]; /* instruction translation table */ void *intc_handle; Modified: trunk/target-sparc/cpu.h =================================================================== --- trunk/target-sparc/cpu.h 2008-07-01 19:28:23 UTC (rev 4816) +++ trunk/target-sparc/cpu.h 2008-07-01 20:01:19 UTC (rev 4817) @@ -215,9 +215,7 @@ uint32_t pil_in; /* incoming interrupt level bitmap */ int psref; /* enable fpu */ target_ulong version; - int user_mode_only; int interrupt_index; - int interrupt_request; uint32_t mmu_bm; uint32_t mmu_ctpr_mask; uint32_t mmu_cxr_mask;