From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43)
	id 1KK9lv-0006fj-G1
	for qemu-devel@nongnu.org; Sat, 19 Jul 2008 06:34:39 -0400
Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43)
	id 1KK9lu-0006fM-AW
	for qemu-devel@nongnu.org; Sat, 19 Jul 2008 06:34:38 -0400
Received: from [199.232.76.173] (port=43653 helo=monty-python.gnu.org)
	by lists.gnu.org with esmtp (Exim 4.43) id 1KK9lu-0006f5-17
	for qemu-devel@nongnu.org; Sat, 19 Jul 2008 06:34:38 -0400
Received: from savannah.gnu.org ([199.232.41.3]:58153 helo=sv.gnu.org)
	by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32)
	(Exim 4.60) (envelope-from <balrogg@gmail.com>) id 1KK9lt-0006gt-LU
	for qemu-devel@nongnu.org; Sat, 19 Jul 2008 06:34:37 -0400
Received: from cvs.savannah.gnu.org ([199.232.41.69])
	by sv.gnu.org with esmtp (Exim 4.63)
	(envelope-from <balrogg@gmail.com>) id 1KK9ls-0002Lm-KR
	for qemu-devel@nongnu.org; Sat, 19 Jul 2008 10:34:36 +0000
Received: from balrog by cvs.savannah.gnu.org with local (Exim 4.63)
	(envelope-from <balrog@savannah.gnu.org>) id 1KK9ls-0002Li-9L
	for qemu-devel@nongnu.org; Sat, 19 Jul 2008 10:34:36 +0000
MIME-Version: 1.0
Errors-To: balrog
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
From: Andrzej Zaborowski <balrogg@gmail.com>
Message-Id: <E1KK9ls-0002Li-9L@cvs.savannah.gnu.org>
Date: Sat, 19 Jul 2008 10:34:36 +0000
Subject: [Qemu-devel] [4899] ARM: fix CPS masks (Vincent Palatin).
Reply-To: qemu-devel@nongnu.org
List-Id: qemu-devel.nongnu.org
List-Unsubscribe: <http://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.gnu.org/pipermail/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <http://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: qemu-devel@nongnu.org

Revision: 4899
          http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=4899
Author:   balrog
Date:     2008-07-19 10:34:35 +0000 (Sat, 19 Jul 2008)

Log Message:
-----------
ARM: fix CPS masks (Vincent Palatin).

According to ARM Reference Manual (DDI0100 A4.1.16),
bit 5 is fixed to 0 (bit 4 is the MSB of the mode), so the instruction mask
should be  0x0ff10020 not 0x0ff10010.
Besides, mmod flag is bit 17 (b14 is SBZ)

Modified Paths:
--------------
    trunk/target-arm/translate.c

Modified: trunk/target-arm/translate.c
===================================================================
--- trunk/target-arm/translate.c	2008-07-19 10:12:22 UTC (rev 4898)
+++ trunk/target-arm/translate.c	2008-07-19 10:34:35 UTC (rev 4899)
@@ -5813,7 +5813,7 @@
             /* Coprocessor double register transfer.  */
         } else if ((insn & 0x0f000010) == 0x0e000010) {
             /* Additional coprocessor register transfer.  */
-        } else if ((insn & 0x0ff10010) == 0x01000000) {
+        } else if ((insn & 0x0ff10020) == 0x01000000) {
             uint32_t mask;
             uint32_t val;
             /* cps (privileged) */
@@ -5830,7 +5830,7 @@
                 if (insn & (1 << 18))
                     val |= mask;
             }
-            if (insn & (1 << 14)) {
+            if (insn & (1 << 17)) {
                 mask |= CPSR_M;
                 val |= (insn & 0x1f);
             }