From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KWIp0-0007qN-IR for qemu-devel@nongnu.org; Thu, 21 Aug 2008 18:40:02 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KWIp0-0007pr-1o for qemu-devel@nongnu.org; Thu, 21 Aug 2008 18:40:02 -0400 Received: from [199.232.76.173] (port=42434 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KWIoz-0007pn-Mr for qemu-devel@nongnu.org; Thu, 21 Aug 2008 18:40:01 -0400 Received: from savannah.gnu.org ([199.232.41.3]:38555 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1KWIoz-0001G0-Aw for qemu-devel@nongnu.org; Thu, 21 Aug 2008 18:40:01 -0400 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.63) (envelope-from ) id 1KWIoy-0002fN-Ly for qemu-devel@nongnu.org; Thu, 21 Aug 2008 22:40:00 +0000 Received: from aliguori by cvs.savannah.gnu.org with local (Exim 4.63) (envelope-from ) id 1KWIoy-0002fJ-EY for qemu-devel@nongnu.org; Thu, 21 Aug 2008 22:40:00 +0000 MIME-Version: 1.0 Errors-To: aliguori Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Anthony Liguori Message-Id: Date: Thu, 21 Aug 2008 22:40:00 +0000 Subject: [Qemu-devel] [5060] Ignore IDE command if issued while IDE is busy (Gleb Natapov) Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 5060 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=5060 Author: aliguori Date: 2008-08-21 22:40:00 +0000 (Thu, 21 Aug 2008) Log Message: ----------- Ignore IDE command if issued while IDE is busy (Gleb Natapov) Feature, Sector Count, LBA Low/Mid/High and Device registers should be written only when both BSY and DRQ are cleared to zero. Command register shall only be written when BSY and DRQ are set to zero for all commands except DEVICE RESET. Data Port register shall be accessed for host PIO data transfer only when DRQ is set to one. Signed-off-by: Gleb Natapov Signed-off-by: Anthony Liguori Modified Paths: -------------- trunk/hw/ide.c Modified: trunk/hw/ide.c =================================================================== --- trunk/hw/ide.c 2008-08-21 22:24:32 UTC (rev 5059) +++ trunk/hw/ide.c 2008-08-21 22:40:00 UTC (rev 5060) @@ -1981,6 +1981,11 @@ #endif addr &= 7; + + /* ignore writes to command block while busy with previous command */ + if (addr != 7 && (ide_if->cur_drive->status & (BUSY_STAT|DRQ_STAT))) + return; + switch(addr) { case 0: break; @@ -2040,6 +2045,10 @@ if (s != ide_if && !s->bs) break; + /* Only DEVICE RESET is allowed while BSY or/and DRQ are set */ + if ((s->status & (BUSY_STAT|DRQ_STAT)) && val != WIN_DEVICE_RESET) + break; + switch(val) { case WIN_IDENTIFY: if (s->bs && !s->is_cdrom) { @@ -2498,6 +2507,10 @@ IDEState *s = ((IDEState *)opaque)->cur_drive; uint8_t *p; + /* PIO data access allowed only when DRQ bit is set */ + if (!(s->status & DRQ_STAT)) + return; + p = s->data_ptr; *(uint16_t *)p = le16_to_cpu(val); p += 2; @@ -2511,6 +2524,11 @@ IDEState *s = ((IDEState *)opaque)->cur_drive; uint8_t *p; int ret; + + /* PIO data access allowed only when DRQ bit is set */ + if (!(s->status & DRQ_STAT)) + return 0; + p = s->data_ptr; ret = cpu_to_le16(*(uint16_t *)p); p += 2; @@ -2525,6 +2543,10 @@ IDEState *s = ((IDEState *)opaque)->cur_drive; uint8_t *p; + /* PIO data access allowed only when DRQ bit is set */ + if (!(s->status & DRQ_STAT)) + return; + p = s->data_ptr; *(uint32_t *)p = le32_to_cpu(val); p += 4; @@ -2539,6 +2561,10 @@ uint8_t *p; int ret; + /* PIO data access allowed only when DRQ bit is set */ + if (!(s->status & DRQ_STAT)) + return 0; + p = s->data_ptr; ret = cpu_to_le32(*(uint32_t *)p); p += 4;