From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KWSSX-0004G7-L1 for qemu-devel@nongnu.org; Fri, 22 Aug 2008 04:57:29 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KWSSW-0004FT-SY for qemu-devel@nongnu.org; Fri, 22 Aug 2008 04:57:29 -0400 Received: from [199.232.76.173] (port=51506 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KWSSW-0004FH-OD for qemu-devel@nongnu.org; Fri, 22 Aug 2008 04:57:28 -0400 Received: from savannah.gnu.org ([199.232.41.3]:49164 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1KWSSW-0001T7-Hq for qemu-devel@nongnu.org; Fri, 22 Aug 2008 04:57:28 -0400 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.63) (envelope-from ) id 1KWSSV-00052C-QS for qemu-devel@nongnu.org; Fri, 22 Aug 2008 08:57:27 +0000 Received: from aurel32 by cvs.savannah.gnu.org with local (Exim 4.63) (envelope-from ) id 1KWSSV-000524-Iw for qemu-devel@nongnu.org; Fri, 22 Aug 2008 08:57:27 +0000 MIME-Version: 1.0 Errors-To: aurel32 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Aurelien Jarno Message-Id: Date: Fri, 22 Aug 2008 08:57:27 +0000 Subject: [Qemu-devel] [5065] [sh4] sleep instruction Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 5065 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=5065 Author: aurel32 Date: 2008-08-22 08:57:27 +0000 (Fri, 22 Aug 2008) Log Message: ----------- [sh4] sleep instruction This patch adds sleep instruction. (Shin-ichiro KAWASAKI) Modified Paths: -------------- trunk/target-sh4/cpu.h trunk/target-sh4/exec.h trunk/target-sh4/helper.c trunk/target-sh4/op.c trunk/target-sh4/translate.c Modified: trunk/target-sh4/cpu.h =================================================================== --- trunk/target-sh4/cpu.h 2008-08-22 08:57:19 UTC (rev 5064) +++ trunk/target-sh4/cpu.h 2008-08-22 08:57:27 UTC (rev 5065) @@ -117,6 +117,7 @@ CPU_COMMON tlb_t utlb[UTLB_SIZE]; /* unified translation table */ tlb_t itlb[ITLB_SIZE]; /* instruction translation table */ void *intc_handle; + int intr_at_halt; /* SR_BL ignored during sleep */ } CPUSH4State; CPUSH4State *cpu_sh4_init(const char *cpu_model); Modified: trunk/target-sh4/exec.h =================================================================== --- trunk/target-sh4/exec.h 2008-08-22 08:57:19 UTC (rev 5064) +++ trunk/target-sh4/exec.h 2008-08-22 08:57:27 UTC (rev 5065) @@ -41,6 +41,7 @@ return 0; if (env->interrupt_request & CPU_INTERRUPT_HARD) { env->halted = 0; + env->intr_at_halt = 1; return 0; } return EXCP_HALTED; Modified: trunk/target-sh4/helper.c =================================================================== --- trunk/target-sh4/helper.c 2008-08-22 08:57:19 UTC (rev 5064) +++ trunk/target-sh4/helper.c 2008-08-22 08:57:27 UTC (rev 5065) @@ -87,9 +87,10 @@ if (do_exp && env->exception_index != 0x1e0) { env->exception_index = 0x000; /* masked exception -> reset */ } - if (do_irq) { + if (do_irq && !env->intr_at_halt) { return; /* masked */ } + env->intr_at_halt = 0; } if (do_irq) { Modified: trunk/target-sh4/op.c =================================================================== --- trunk/target-sh4/op.c 2008-08-22 08:57:19 UTC (rev 5064) +++ trunk/target-sh4/op.c 2008-08-22 08:57:27 UTC (rev 5065) @@ -1091,6 +1091,13 @@ cpu_loop_exit(); } +void OPPROTO op_sleep(void) +{ + env->halted = 1; + env->exception_index = EXCP_HLT; + cpu_loop_exit(); +} + /* Load and store */ #define MEMSUFFIX _raw #include "op_mem.c" Modified: trunk/target-sh4/translate.c =================================================================== --- trunk/target-sh4/translate.c 2008-08-22 08:57:19 UTC (rev 5064) +++ trunk/target-sh4/translate.c 2008-08-22 08:57:27 UTC (rev 5065) @@ -298,7 +298,12 @@ case 0x0009: /* nop */ return; case 0x001b: /* sleep */ - assert(0); /* XXXXX */ + if (ctx->memidx) { + gen_op_sleep(); + } else { + gen_op_raise_illegal_instruction(); + ctx->bstate = BS_EXCP; + } return; }