From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KZB82-00071d-RP for qemu-devel@nongnu.org; Fri, 29 Aug 2008 17:03:34 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KZB80-0006zE-Uw for qemu-devel@nongnu.org; Fri, 29 Aug 2008 17:03:33 -0400 Received: from [199.232.76.173] (port=46629 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KZB80-0006z5-JO for qemu-devel@nongnu.org; Fri, 29 Aug 2008 17:03:32 -0400 Received: from savannah.gnu.org ([199.232.41.3]:38877 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1KZB80-0005aI-9Z for qemu-devel@nongnu.org; Fri, 29 Aug 2008 17:03:32 -0400 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.63) (envelope-from ) id 1KZB7z-0000IF-P7 for qemu-devel@nongnu.org; Fri, 29 Aug 2008 21:03:31 +0000 Received: from blueswir1 by cvs.savannah.gnu.org with local (Exim 4.63) (envelope-from ) id 1KZB7z-0000IB-Fz for qemu-devel@nongnu.org; Fri, 29 Aug 2008 21:03:31 +0000 MIME-Version: 1.0 Errors-To: blueswir1 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Blue Swirl Message-Id: Date: Fri, 29 Aug 2008 21:03:31 +0000 Subject: [Qemu-devel] [5110] Fix FCC handling for Sparc64 target, initial patch by Vince Weaver Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 5110 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=5110 Author: blueswir1 Date: 2008-08-29 21:03:31 +0000 (Fri, 29 Aug 2008) Log Message: ----------- Fix FCC handling for Sparc64 target, initial patch by Vince Weaver Modified Paths: -------------- trunk/target-sparc/cpu.h trunk/target-sparc/translate.c Modified: trunk/target-sparc/cpu.h =================================================================== --- trunk/target-sparc/cpu.h 2008-08-29 20:50:21 UTC (rev 5109) +++ trunk/target-sparc/cpu.h 2008-08-29 21:03:31 UTC (rev 5110) @@ -110,48 +110,48 @@ #endif /* Fcc */ -#define FSR_RD1 (1<<31) -#define FSR_RD0 (1<<30) +#define FSR_RD1 (1ULL << 31) +#define FSR_RD0 (1ULL << 30) #define FSR_RD_MASK (FSR_RD1 | FSR_RD0) #define FSR_RD_NEAREST 0 #define FSR_RD_ZERO FSR_RD0 #define FSR_RD_POS FSR_RD1 #define FSR_RD_NEG (FSR_RD1 | FSR_RD0) -#define FSR_NVM (1<<27) -#define FSR_OFM (1<<26) -#define FSR_UFM (1<<25) -#define FSR_DZM (1<<24) -#define FSR_NXM (1<<23) +#define FSR_NVM (1ULL << 27) +#define FSR_OFM (1ULL << 26) +#define FSR_UFM (1ULL << 25) +#define FSR_DZM (1ULL << 24) +#define FSR_NXM (1ULL << 23) #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM) -#define FSR_NVA (1<<9) -#define FSR_OFA (1<<8) -#define FSR_UFA (1<<7) -#define FSR_DZA (1<<6) -#define FSR_NXA (1<<5) +#define FSR_NVA (1ULL << 9) +#define FSR_OFA (1ULL << 8) +#define FSR_UFA (1ULL << 7) +#define FSR_DZA (1ULL << 6) +#define FSR_NXA (1ULL << 5) #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) -#define FSR_NVC (1<<4) -#define FSR_OFC (1<<3) -#define FSR_UFC (1<<2) -#define FSR_DZC (1<<1) -#define FSR_NXC (1<<0) +#define FSR_NVC (1ULL << 4) +#define FSR_OFC (1ULL << 3) +#define FSR_UFC (1ULL << 2) +#define FSR_DZC (1ULL << 1) +#define FSR_NXC (1ULL << 0) #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC) -#define FSR_FTT2 (1<<16) -#define FSR_FTT1 (1<<15) -#define FSR_FTT0 (1<<14) +#define FSR_FTT2 (1ULL << 16) +#define FSR_FTT1 (1ULL << 15) +#define FSR_FTT0 (1ULL << 14) #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0) -#define FSR_FTT_IEEE_EXCP (1 << 14) -#define FSR_FTT_UNIMPFPOP (3 << 14) -#define FSR_FTT_SEQ_ERROR (4 << 14) -#define FSR_FTT_INVAL_FPR (6 << 14) +#define FSR_FTT_IEEE_EXCP (1ULL << 14) +#define FSR_FTT_UNIMPFPOP (3ULL << 14) +#define FSR_FTT_SEQ_ERROR (4ULL << 14) +#define FSR_FTT_INVAL_FPR (6ULL << 14) #define FSR_FCC1_SHIFT 11 -#define FSR_FCC1 (1 << FSR_FCC1_SHIFT) +#define FSR_FCC1 (1ULL << FSR_FCC1_SHIFT) #define FSR_FCC0_SHIFT 10 -#define FSR_FCC0 (1 << FSR_FCC0_SHIFT) +#define FSR_FCC0 (1ULL << FSR_FCC0_SHIFT) /* MMU */ #define MMU_E (1<<0) Modified: trunk/target-sparc/translate.c =================================================================== --- trunk/target-sparc/translate.c 2008-08-29 20:50:21 UTC (rev 5109) +++ trunk/target-sparc/translate.c 2008-08-29 21:03:31 UTC (rev 5110) @@ -999,16 +999,14 @@ static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src, unsigned int fcc_offset) { - tcg_gen_extu_i32_tl(reg, src); - tcg_gen_shri_tl(reg, reg, FSR_FCC0_SHIFT + fcc_offset); + tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset); tcg_gen_andi_tl(reg, reg, 0x1); } static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src, unsigned int fcc_offset) { - tcg_gen_extu_i32_tl(reg, src); - tcg_gen_shri_tl(reg, reg, FSR_FCC1_SHIFT + fcc_offset); + tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset); tcg_gen_andi_tl(reg, reg, 0x1); }