From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KaFBV-0004ff-FV for qemu-devel@nongnu.org; Mon, 01 Sep 2008 15:35:33 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KaFBV-0004fM-0M for qemu-devel@nongnu.org; Mon, 01 Sep 2008 15:35:33 -0400 Received: from [199.232.76.173] (port=33277 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KaFBU-0004fG-Lo for qemu-devel@nongnu.org; Mon, 01 Sep 2008 15:35:32 -0400 Received: from savannah.gnu.org ([199.232.41.3]:39715 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1KaFBU-0007kk-3K for qemu-devel@nongnu.org; Mon, 01 Sep 2008 15:35:32 -0400 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.63) (envelope-from ) id 1KaFBT-0003Do-9W for qemu-devel@nongnu.org; Mon, 01 Sep 2008 19:35:31 +0000 Received: from blueswir1 by cvs.savannah.gnu.org with local (Exim 4.63) (envelope-from ) id 1KaFBS-0003DQ-SJ for qemu-devel@nongnu.org; Mon, 01 Sep 2008 19:35:31 +0000 MIME-Version: 1.0 Errors-To: blueswir1 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Blue Swirl Message-Id: Date: Mon, 01 Sep 2008 19:35:30 +0000 Subject: [Qemu-devel] [5123] Fix y register loads and stores Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 5123 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=5123 Author: blueswir1 Date: 2008-09-01 19:35:29 +0000 (Mon, 01 Sep 2008) Log Message: ----------- Fix y register loads and stores Modified Paths: -------------- trunk/target-sparc/translate.c Modified: trunk/target-sparc/translate.c =================================================================== --- trunk/target-sparc/translate.c 2008-09-01 13:09:21 UTC (rev 5122) +++ trunk/target-sparc/translate.c 2008-09-01 19:35:29 UTC (rev 5123) @@ -713,36 +713,32 @@ static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2) { - TCGv r_temp, r_temp2; + TCGv r_temp; int l1; l1 = gen_new_label(); r_temp = tcg_temp_new(TCG_TYPE_TL); - r_temp2 = tcg_temp_new(TCG_TYPE_I32); /* old op: if (!(env->y & 1)) T1 = 0; */ tcg_gen_mov_tl(cpu_cc_src, src1); - tcg_gen_ld32u_tl(r_temp, cpu_env, offsetof(CPUSPARCState, y)); - tcg_gen_trunc_tl_i32(r_temp2, r_temp); - tcg_gen_andi_i32(r_temp2, r_temp2, 0x1); + tcg_gen_ld_tl(r_temp, cpu_env, offsetof(CPUSPARCState, y)); + tcg_gen_andi_tl(r_temp, r_temp, 0x1); tcg_gen_mov_tl(cpu_cc_src2, src2); - tcg_gen_brcondi_i32(TCG_COND_NE, r_temp2, 0, l1); + tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1); tcg_gen_movi_tl(cpu_cc_src2, 0); gen_set_label(l1); // b2 = T0 & 1; // env->y = (b2 << 31) | (env->y >> 1); - tcg_gen_trunc_tl_i32(r_temp2, cpu_cc_src); - tcg_gen_andi_i32(r_temp2, r_temp2, 0x1); - tcg_gen_shli_i32(r_temp2, r_temp2, 31); - tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y)); - tcg_gen_shri_i32(cpu_tmp32, cpu_tmp32, 1); - tcg_gen_or_i32(cpu_tmp32, cpu_tmp32, r_temp2); - tcg_temp_free(r_temp2); - tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y)); + tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1); + tcg_gen_shli_tl(r_temp, r_temp, 31); + tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, y)); + tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 1); + tcg_gen_or_tl(cpu_tmp0, cpu_tmp0, r_temp); + tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, y)); // b1 = N ^ V; gen_mov_reg_N(cpu_tmp0, cpu_psr); @@ -778,9 +774,10 @@ tcg_gen_mul_i64(r_temp2, r_temp, r_temp2); tcg_gen_shri_i64(r_temp, r_temp2, 32); - tcg_gen_trunc_i64_i32(r_temp, r_temp); - tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y)); + tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp); tcg_temp_free(r_temp); + tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffff); + tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, y)); #ifdef TARGET_SPARC64 tcg_gen_mov_i64(dst, r_temp2); #else @@ -801,9 +798,10 @@ tcg_gen_mul_i64(r_temp2, r_temp, r_temp2); tcg_gen_shri_i64(r_temp, r_temp2, 32); - tcg_gen_trunc_i64_i32(r_temp, r_temp); - tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y)); + tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp); tcg_temp_free(r_temp); + tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffff); + tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, y)); #ifdef TARGET_SPARC64 tcg_gen_mov_i64(dst, r_temp2); #else