From: Blue Swirl <blauwirbel@gmail.com>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [5175] Silence gcc warning about constant overflow
Date: Sat, 06 Sep 2008 17:50:17 +0000 [thread overview]
Message-ID: <E1Kc1vN-0005Hj-4E@cvs.savannah.gnu.org> (raw)
Revision: 5175
http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=5175
Author: blueswir1
Date: 2008-09-06 17:50:16 +0000 (Sat, 06 Sep 2008)
Log Message:
-----------
Silence gcc warning about constant overflow
Modified Paths:
--------------
trunk/target-sparc/cpu.h
trunk/target-sparc/translate.c
Modified: trunk/target-sparc/cpu.h
===================================================================
--- trunk/target-sparc/cpu.h 2008-09-06 17:49:06 UTC (rev 5174)
+++ trunk/target-sparc/cpu.h 2008-09-06 17:50:16 UTC (rev 5175)
@@ -142,7 +142,15 @@
#define FSR_FTT2 (1ULL << 16)
#define FSR_FTT1 (1ULL << 15)
#define FSR_FTT0 (1ULL << 14)
-#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
+//gcc warns about constant overflow for ~FSR_FTT_MASK
+//#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
+#ifdef TARGET_SPARC64
+#define FSR_FTT_NMASK 0xfffffffffffe3fffULL
+#define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL
+#else
+#define FSR_FTT_NMASK 0xfffe3fffULL
+#define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL
+#endif
#define FSR_FTT_IEEE_EXCP (1ULL << 14)
#define FSR_FTT_UNIMPFPOP (3ULL << 14)
#define FSR_FTT_SEQ_ERROR (4ULL << 14)
Modified: trunk/target-sparc/translate.c
===================================================================
--- trunk/target-sparc/translate.c 2008-09-06 17:49:06 UTC (rev 5174)
+++ trunk/target-sparc/translate.c 2008-09-06 17:50:16 UTC (rev 5175)
@@ -1602,7 +1602,7 @@
{
TCGv r_const;
- tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK);
+ tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK);
tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
r_const = tcg_const_i32(TT_FP_EXCP);
tcg_gen_helper_0_1(raise_exception, r_const);
@@ -1628,7 +1628,7 @@
static inline void gen_op_clear_ieee_excp_and_FTT(void)
{
- tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~(FSR_FTT_MASK | FSR_CEXC_MASK));
+ tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK);
}
static inline void gen_clear_float_exceptions(void)
reply other threads:[~2008-09-06 17:50 UTC|newest]
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