From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KdVp0-0007kT-0B for qemu-devel@nongnu.org; Wed, 10 Sep 2008 15:57:50 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KdVoz-0007k2-HX for qemu-devel@nongnu.org; Wed, 10 Sep 2008 15:57:49 -0400 Received: from [199.232.76.173] (port=55558 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KdVoy-0007jq-S5 for qemu-devel@nongnu.org; Wed, 10 Sep 2008 15:57:48 -0400 Received: from savannah.gnu.org ([199.232.41.3]:33389 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1KdVow-00068J-7k for qemu-devel@nongnu.org; Wed, 10 Sep 2008 15:57:48 -0400 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.63) (envelope-from ) id 1KdVom-0001au-Q5 for qemu-devel@nongnu.org; Wed, 10 Sep 2008 19:57:36 +0000 Received: from blueswir1 by cvs.savannah.gnu.org with local (Exim 4.63) (envelope-from ) id 1KdVom-0001aq-7g for qemu-devel@nongnu.org; Wed, 10 Sep 2008 19:57:36 +0000 MIME-Version: 1.0 Errors-To: blueswir1 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Blue Swirl Message-Id: Date: Wed, 10 Sep 2008 19:57:36 +0000 Subject: [Qemu-devel] [5191] Convert basic 64 bit VIS ops to TCG Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 5191 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=5191 Author: blueswir1 Date: 2008-09-10 19:57:35 +0000 (Wed, 10 Sep 2008) Log Message: ----------- Convert basic 64 bit VIS ops to TCG Modified Paths: -------------- trunk/target-sparc/TODO trunk/target-sparc/helper.h trunk/target-sparc/op_helper.c trunk/target-sparc/translate.c Modified: trunk/target-sparc/TODO =================================================================== --- trunk/target-sparc/TODO 2008-09-10 19:57:13 UTC (rev 5190) +++ trunk/target-sparc/TODO 2008-09-10 19:57:35 UTC (rev 5191) @@ -39,8 +39,6 @@ - Full hypervisor support - SMP/CMT - Sun4v CPUs -- Optimizations/improvements: - - Use TCG logic ops for VIS when possible Sun4: - To be added Modified: trunk/target-sparc/helper.h =================================================================== --- trunk/target-sparc/helper.h 2008-09-10 19:57:13 UTC (rev 5190) +++ trunk/target-sparc/helper.h 2008-09-10 19:57:35 UTC (rev 5191) @@ -139,15 +139,6 @@ F_HELPER_0_0(qtox); F_HELPER_0_0(aligndata); -F_HELPER_0_0(not); -F_HELPER_0_0(nor); -F_HELPER_0_0(or); -F_HELPER_0_0(xor); -F_HELPER_0_0(and); -F_HELPER_0_0(ornot); -F_HELPER_0_0(andnot); -F_HELPER_0_0(nand); -F_HELPER_0_0(xnor); F_HELPER_0_0(pmerge); F_HELPER_0_0(mul8x16); F_HELPER_0_0(mul8x16al); Modified: trunk/target-sparc/op_helper.c =================================================================== --- trunk/target-sparc/op_helper.c 2008-09-10 19:57:13 UTC (rev 5190) +++ trunk/target-sparc/op_helper.c 2008-09-10 19:57:35 UTC (rev 5191) @@ -246,51 +246,6 @@ *((uint64_t *)&DT0) = tmp; } -void helper_fnot(void) -{ - *(uint64_t *)&DT0 = ~*(uint64_t *)&DT1; -} - -void helper_fnor(void) -{ - *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 | *(uint64_t *)&DT1); -} - -void helper_for(void) -{ - *(uint64_t *)&DT0 |= *(uint64_t *)&DT1; -} - -void helper_fxor(void) -{ - *(uint64_t *)&DT0 ^= *(uint64_t *)&DT1; -} - -void helper_fand(void) -{ - *(uint64_t *)&DT0 &= *(uint64_t *)&DT1; -} - -void helper_fornot(void) -{ - *(uint64_t *)&DT0 = *(uint64_t *)&DT0 | ~*(uint64_t *)&DT1; -} - -void helper_fandnot(void) -{ - *(uint64_t *)&DT0 = *(uint64_t *)&DT0 & ~*(uint64_t *)&DT1; -} - -void helper_fnand(void) -{ - *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 & *(uint64_t *)&DT1); -} - -void helper_fxnor(void) -{ - *(uint64_t *)&DT0 ^= ~*(uint64_t *)&DT1; -} - #ifdef WORDS_BIGENDIAN #define VIS_B64(n) b[7 - (n)] #define VIS_W64(n) w[3 - (n)] Modified: trunk/target-sparc/translate.c =================================================================== --- trunk/target-sparc/translate.c 2008-09-10 19:57:13 UTC (rev 5190) +++ trunk/target-sparc/translate.c 2008-09-10 19:57:35 UTC (rev 5191) @@ -3886,10 +3886,12 @@ break; case 0x062: /* VIS I fnor */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fnor); - gen_op_store_DT0_fpr(DFPREG(rd)); + tcg_gen_or_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], + cpu_fpr[DFPREG(rs2)]); + tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, -1); + tcg_gen_or_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1], + cpu_fpr[DFPREG(rs2) + 1]); + tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, -1); break; case 0x063: /* VIS I fnors */ CHECK_FPU_FEATURE(dc, VIS1); @@ -3898,10 +3900,12 @@ break; case 0x064: /* VIS I fandnot2 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT1(DFPREG(rs1)); - gen_op_load_fpr_DT0(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fandnot); - gen_op_store_DT0_fpr(DFPREG(rd)); + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], -1); + tcg_gen_and_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, + cpu_fpr[DFPREG(rs2)]); + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1], -1); + tcg_gen_and_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, + cpu_fpr[DFPREG(rs2) + 1]); break; case 0x065: /* VIS I fandnot2s */ CHECK_FPU_FEATURE(dc, VIS1); @@ -3910,9 +3914,10 @@ break; case 0x066: /* VIS I fnot2 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fnot); - gen_op_store_DT0_fpr(DFPREG(rd)); + tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)], + -1); + tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1], + cpu_fpr[DFPREG(rs2) + 1], -1); break; case 0x067: /* VIS I fnot2s */ CHECK_FPU_FEATURE(dc, VIS1); @@ -3920,10 +3925,12 @@ break; case 0x068: /* VIS I fandnot1 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fandnot); - gen_op_store_DT0_fpr(DFPREG(rd)); + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1); + tcg_gen_and_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, + cpu_fpr[DFPREG(rs1)]); + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1); + tcg_gen_and_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, + cpu_fpr[DFPREG(rs1) + 1]); break; case 0x069: /* VIS I fandnot1s */ CHECK_FPU_FEATURE(dc, VIS1); @@ -3932,9 +3939,10 @@ break; case 0x06a: /* VIS I fnot1 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT1(DFPREG(rs1)); - tcg_gen_helper_0_0(helper_fnot); - gen_op_store_DT0_fpr(DFPREG(rd)); + tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], + -1); + tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1], + cpu_fpr[DFPREG(rs1) + 1], -1); break; case 0x06b: /* VIS I fnot1s */ CHECK_FPU_FEATURE(dc, VIS1); @@ -3942,10 +3950,11 @@ break; case 0x06c: /* VIS I fxor */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fxor); - gen_op_store_DT0_fpr(DFPREG(rd)); + tcg_gen_xor_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], + cpu_fpr[DFPREG(rs2)]); + tcg_gen_xor_i32(cpu_fpr[DFPREG(rd) + 1], + cpu_fpr[DFPREG(rs1) + 1], + cpu_fpr[DFPREG(rs2) + 1]); break; case 0x06d: /* VIS I fxors */ CHECK_FPU_FEATURE(dc, VIS1); @@ -3953,10 +3962,12 @@ break; case 0x06e: /* VIS I fnand */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fnand); - gen_op_store_DT0_fpr(DFPREG(rd)); + tcg_gen_and_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], + cpu_fpr[DFPREG(rs2)]); + tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, -1); + tcg_gen_and_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1], + cpu_fpr[DFPREG(rs2) + 1]); + tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, -1); break; case 0x06f: /* VIS I fnands */ CHECK_FPU_FEATURE(dc, VIS1); @@ -3965,10 +3976,11 @@ break; case 0x070: /* VIS I fand */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fand); - gen_op_store_DT0_fpr(DFPREG(rd)); + tcg_gen_and_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], + cpu_fpr[DFPREG(rs2)]); + tcg_gen_and_i32(cpu_fpr[DFPREG(rd) + 1], + cpu_fpr[DFPREG(rs1) + 1], + cpu_fpr[DFPREG(rs2) + 1]); break; case 0x071: /* VIS I fands */ CHECK_FPU_FEATURE(dc, VIS1); @@ -3976,10 +3988,12 @@ break; case 0x072: /* VIS I fxnor */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fxnor); - gen_op_store_DT0_fpr(DFPREG(rd)); + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1); + tcg_gen_xor_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, + cpu_fpr[DFPREG(rs1)]); + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2) + 1], -1); + tcg_gen_xor_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, + cpu_fpr[DFPREG(rs1) + 1]); break; case 0x073: /* VIS I fxnors */ CHECK_FPU_FEATURE(dc, VIS1); @@ -3998,10 +4012,12 @@ break; case 0x076: /* VIS I fornot2 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT1(DFPREG(rs1)); - gen_op_load_fpr_DT0(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fornot); - gen_op_store_DT0_fpr(DFPREG(rd)); + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], -1); + tcg_gen_or_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, + cpu_fpr[DFPREG(rs2)]); + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1], -1); + tcg_gen_or_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, + cpu_fpr[DFPREG(rs2) + 1]); break; case 0x077: /* VIS I fornot2s */ CHECK_FPU_FEATURE(dc, VIS1); @@ -4019,10 +4035,12 @@ break; case 0x07a: /* VIS I fornot1 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fornot); - gen_op_store_DT0_fpr(DFPREG(rd)); + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1); + tcg_gen_or_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, + cpu_fpr[DFPREG(rs1)]); + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2) + 1], -1); + tcg_gen_or_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, + cpu_fpr[DFPREG(rs1) + 1]); break; case 0x07b: /* VIS I fornot1s */ CHECK_FPU_FEATURE(dc, VIS1); @@ -4031,10 +4049,11 @@ break; case 0x07c: /* VIS I for */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_for); - gen_op_store_DT0_fpr(DFPREG(rd)); + tcg_gen_or_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], + cpu_fpr[DFPREG(rs2)]); + tcg_gen_or_i32(cpu_fpr[DFPREG(rd) + 1], + cpu_fpr[DFPREG(rs1) + 1], + cpu_fpr[DFPREG(rs2) + 1]); break; case 0x07d: /* VIS I fors */ CHECK_FPU_FEATURE(dc, VIS1);