From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Kg58h-00046o-Mq for qemu-devel@nongnu.org; Wed, 17 Sep 2008 18:04:47 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Kg58g-00045q-LS for qemu-devel@nongnu.org; Wed, 17 Sep 2008 18:04:47 -0400 Received: from [199.232.76.173] (port=35151 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Kg58g-00045d-GT for qemu-devel@nongnu.org; Wed, 17 Sep 2008 18:04:46 -0400 Received: from savannah.gnu.org ([199.232.41.3]:58461 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1Kg58g-0000bl-0m for qemu-devel@nongnu.org; Wed, 17 Sep 2008 18:04:46 -0400 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.63) (envelope-from ) id 1Kg58f-0001fA-Ef for qemu-devel@nongnu.org; Wed, 17 Sep 2008 22:04:45 +0000 Received: from aurel32 by cvs.savannah.gnu.org with local (Exim 4.63) (envelope-from ) id 1Kg58f-0001f6-6C for qemu-devel@nongnu.org; Wed, 17 Sep 2008 22:04:45 +0000 MIME-Version: 1.0 Errors-To: aurel32 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Aurelien Jarno Message-Id: Date: Wed, 17 Sep 2008 22:04:45 +0000 Subject: [Qemu-devel] [5245] alpha: convert cmov and bcond to TCG Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 5245 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=5245 Author: aurel32 Date: 2008-09-17 22:04:44 +0000 (Wed, 17 Sep 2008) Log Message: ----------- alpha: convert cmov and bcond to TCG Patch mostly by Tristan Gingold Modified Paths: -------------- trunk/target-alpha/op.c trunk/target-alpha/op_template.h trunk/target-alpha/translate.c Modified: trunk/target-alpha/op.c =================================================================== --- trunk/target-alpha/op.c 2008-09-17 22:04:37 UTC (rev 5244) +++ trunk/target-alpha/op.c 2008-09-17 22:04:44 UTC (rev 5245) @@ -434,72 +434,6 @@ RETURN(); } -void OPPROTO op_cmpeqz (void) -{ - if (T0 == 0) - T0 = 1; - else - T0 = 0; - RETURN(); -} - -void OPPROTO op_cmpnez (void) -{ - if (T0 != 0) - T0 = 1; - else - T0 = 0; - RETURN(); -} - -void OPPROTO op_cmpltz (void) -{ - if ((int64_t)T0 < 0) - T0 = 1; - else - T0 = 0; - RETURN(); -} - -void OPPROTO op_cmplez (void) -{ - if ((int64_t)T0 <= 0) - T0 = 1; - else - T0 = 0; - RETURN(); -} - -void OPPROTO op_cmpgtz (void) -{ - if ((int64_t)T0 > 0) - T0 = 1; - else - T0 = 0; - RETURN(); -} - -void OPPROTO op_cmpgez (void) -{ - if ((int64_t)T0 >= 0) - T0 = 1; - else - T0 = 0; - RETURN(); -} - -void OPPROTO op_cmplbs (void) -{ - T0 &= 1; - RETURN(); -} - -void OPPROTO op_cmplbc (void) -{ - T0 = (~T0) & 1; - RETURN(); -} - #if 0 // Qemu does not know how to do this... void OPPROTO op_bcond (void) { Modified: trunk/target-alpha/op_template.h =================================================================== --- trunk/target-alpha/op_template.h 2008-09-17 22:04:37 UTC (rev 5244) +++ trunk/target-alpha/op_template.h 2008-09-17 22:04:44 UTC (rev 5245) @@ -37,15 +37,7 @@ #endif /* REG < 3 */ -/* Fixed-point register moves */ #if REG < 31 -void OPPROTO glue(op_cmov_ir, REG) (void) -{ - if (T0) - env->ir[REG] = T1; - RETURN(); -} - /* floating point registers moves */ void OPPROTO glue(op_load_FT0_fir, REG) (void) { Modified: trunk/target-alpha/translate.c =================================================================== --- trunk/target-alpha/translate.c 2008-09-17 22:04:37 UTC (rev 5244) +++ trunk/target-alpha/translate.c 2008-09-17 22:04:44 UTC (rev 5245) @@ -124,11 +124,6 @@ NAME ## _table[n](); \ } -/* IR moves */ -/* Special hacks for ir31 */ -#define gen_op_cmov_ir31 gen_op_nop -GEN32(gen_op_cmov_ir, gen_op_cmov_ir); - /* FIR moves */ /* Special hacks for fir31 */ #define gen_op_load_FT0_fir31 gen_op_reset_FT0 @@ -328,16 +323,32 @@ } static always_inline void gen_bcond (DisasContext *ctx, - void (*gen_test_op)(void), - int ra, int32_t disp16) + TCGCond cond, + int ra, int32_t disp16, int mask) { - tcg_gen_movi_i64(cpu_T[1], ctx->pc + (int64_t)(disp16 << 2)); - if (ra != 31) - tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]); - else - tcg_gen_movi_i64(cpu_T[0], 0); - (*gen_test_op)(); - _gen_op_bcond(ctx); + int l1, l2; + + l1 = gen_new_label(); + l2 = gen_new_label(); + if (likely(ra != 31)) { + if (mask) { + TCGv tmp = tcg_temp_new(TCG_TYPE_I64); + tcg_gen_andi_i64(tmp, cpu_ir[ra], 1); + tcg_gen_brcondi_i64(cond, tmp, 0, l1); + tcg_temp_free(tmp); + } else + tcg_gen_brcondi_i64(cond, cpu_ir[ra], 0, l1); + } else { + /* Very uncommon case - Do not bother to optimize. */ + TCGv tmp = tcg_const_i64(0); + tcg_gen_brcondi_i64(cond, tmp, 0, l1); + tcg_temp_free(tmp); + } + tcg_gen_movi_i64(cpu_pc, ctx->pc); + tcg_gen_br(l2); + gen_set_label(l1); + tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp16 << 2)); + gen_set_label(l2); } static always_inline void gen_fbcond (DisasContext *ctx, @@ -371,22 +382,39 @@ } static always_inline void gen_cmov (DisasContext *ctx, - void (*gen_test_op)(void), + TCGCond inv_cond, int ra, int rb, int rc, - int islit, uint8_t lit) + int islit, int8_t lit, int mask) { - if (ra != 31) - tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]); - else - tcg_gen_movi_i64(cpu_T[0], 0); + int l1; + + if (unlikely(rc == 31)) + return; + + l1 = gen_new_label(); + + if (ra != 31) { + if (mask) { + TCGv tmp = tcg_temp_new(TCG_TYPE_I64); + tcg_gen_andi_i64(tmp, cpu_ir[ra], 1); + tcg_gen_brcondi_i64(inv_cond, tmp, 0, l1); + tcg_temp_free(tmp); + } else + tcg_gen_brcondi_i64(inv_cond, cpu_ir[ra], 0, l1); + } else { + /* Very uncommon case - Do not bother to optimize. */ + TCGv tmp = tcg_const_i64(0); + tcg_gen_brcondi_i64(inv_cond, tmp, 0, l1); + tcg_temp_free(tmp); + } + if (islit) - tcg_gen_movi_i64(cpu_T[1], lit); + tcg_gen_movi_i64(cpu_ir[rc], lit); else if (rb != 31) - tcg_gen_mov_i64(cpu_T[1], cpu_ir[rb]); + tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); else - tcg_gen_movi_i64(cpu_T[1], 0); - (*gen_test_op)(); - gen_op_cmov_ir(rc); + tcg_gen_movi_i64(cpu_ir[rc], 0); + gen_set_label(l1); } static always_inline void gen_farith2 (DisasContext *ctx, @@ -933,11 +961,11 @@ break; case 0x14: /* CMOVLBS */ - gen_cmov(ctx, &gen_op_cmplbs, ra, rb, rc, islit, lit); + gen_cmov(ctx, TCG_COND_EQ, ra, rb, rc, islit, lit, 1); break; case 0x16: /* CMOVLBC */ - gen_cmov(ctx, &gen_op_cmplbc, ra, rb, rc, islit, lit); + gen_cmov(ctx, TCG_COND_NE, ra, rb, rc, islit, lit, 1); break; case 0x20: /* BIS */ @@ -961,11 +989,11 @@ break; case 0x24: /* CMOVEQ */ - gen_cmov(ctx, &gen_op_cmpeqz, ra, rb, rc, islit, lit); + gen_cmov(ctx, TCG_COND_NE, ra, rb, rc, islit, lit, 0); break; case 0x26: /* CMOVNE */ - gen_cmov(ctx, &gen_op_cmpnez, ra, rb, rc, islit, lit); + gen_cmov(ctx, TCG_COND_EQ, ra, rb, rc, islit, lit, 0); break; case 0x28: /* ORNOT */ @@ -1011,11 +1039,11 @@ break; case 0x44: /* CMOVLT */ - gen_cmov(ctx, &gen_op_cmpltz, ra, rb, rc, islit, lit); + gen_cmov(ctx, TCG_COND_GE, ra, rb, rc, islit, lit, 0); break; case 0x46: /* CMOVGE */ - gen_cmov(ctx, &gen_op_cmpgez, ra, rb, rc, islit, lit); + gen_cmov(ctx, TCG_COND_LT, ra, rb, rc, islit, lit, 0); break; case 0x48: /* EQV */ @@ -1053,11 +1081,11 @@ break; case 0x64: /* CMOVLE */ - gen_cmov(ctx, &gen_op_cmplez, ra, rb, rc, islit, lit); + gen_cmov(ctx, TCG_COND_GT, ra, rb, rc, islit, lit, 0); break; case 0x66: /* CMOVGT */ - gen_cmov(ctx, &gen_op_cmpgtz, ra, rb, rc, islit, lit); + gen_cmov(ctx, TCG_COND_LE, ra, rb, rc, islit, lit, 0); break; case 0x6C: /* IMPLVER */ @@ -2173,42 +2201,42 @@ break; case 0x38: /* BLBC */ - gen_bcond(ctx, &gen_op_cmplbc, ra, disp16); + gen_bcond(ctx, TCG_COND_EQ, ra, disp16, 1); ret = 1; break; case 0x39: /* BEQ */ - gen_bcond(ctx, &gen_op_cmpeqz, ra, disp16); + gen_bcond(ctx, TCG_COND_EQ, ra, disp16, 0); ret = 1; break; case 0x3A: /* BLT */ - gen_bcond(ctx, &gen_op_cmpltz, ra, disp16); + gen_bcond(ctx, TCG_COND_LT, ra, disp16, 0); ret = 1; break; case 0x3B: /* BLE */ - gen_bcond(ctx, &gen_op_cmplez, ra, disp16); + gen_bcond(ctx, TCG_COND_LE, ra, disp16, 0); ret = 1; break; case 0x3C: /* BLBS */ - gen_bcond(ctx, &gen_op_cmplbs, ra, disp16); + gen_bcond(ctx, TCG_COND_NE, ra, disp16, 1); ret = 1; break; case 0x3D: /* BNE */ - gen_bcond(ctx, &gen_op_cmpnez, ra, disp16); + gen_bcond(ctx, TCG_COND_NE, ra, disp16, 0); ret = 1; break; case 0x3E: /* BGE */ - gen_bcond(ctx, &gen_op_cmpgez, ra, disp16); + gen_bcond(ctx, TCG_COND_GE, ra, disp16, 0); ret = 1; break; case 0x3F: /* BGT */ - gen_bcond(ctx, &gen_op_cmpgtz, ra, disp16); + gen_bcond(ctx, TCG_COND_GT, ra, disp16, 0); ret = 1; break; invalid_opc: