From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KhPIi-0000xk-Qc for qemu-devel@nongnu.org; Sun, 21 Sep 2008 09:48:36 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KhPIh-0000xU-1Q for qemu-devel@nongnu.org; Sun, 21 Sep 2008 09:48:36 -0400 Received: from [199.232.76.173] (port=46556 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KhPIg-0000xR-RS for qemu-devel@nongnu.org; Sun, 21 Sep 2008 09:48:34 -0400 Received: from savannah.gnu.org ([199.232.41.3]:36895 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1KhPIg-0004S8-D6 for qemu-devel@nongnu.org; Sun, 21 Sep 2008 09:48:34 -0400 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.63) (envelope-from ) id 1KhPIf-0005Ad-Qs for qemu-devel@nongnu.org; Sun, 21 Sep 2008 13:48:33 +0000 Received: from pbrook by cvs.savannah.gnu.org with local (Exim 4.63) (envelope-from ) id 1KhPIf-0005AZ-4a for qemu-devel@nongnu.org; Sun, 21 Sep 2008 13:48:33 +0000 MIME-Version: 1.0 Errors-To: pbrook Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Paul Brook Message-Id: Date: Sun, 21 Sep 2008 13:48:33 +0000 Subject: [Qemu-devel] [5280] Add concat_i32_i64 op. Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 5280 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=5280 Author: pbrook Date: 2008-09-21 13:48:32 +0000 (Sun, 21 Sep 2008) Log Message: ----------- Add concat_i32_i64 op. Modified Paths: -------------- trunk/target-arm/translate.c trunk/target-mips/translate.c trunk/target-ppc/translate.c trunk/target-sh4/translate.c trunk/tcg/README trunk/tcg/tcg-op.h Modified: trunk/target-arm/translate.c =================================================================== --- trunk/target-arm/translate.c 2008-09-21 02:39:45 UTC (rev 5279) +++ trunk/target-arm/translate.c 2008-09-21 13:48:32 UTC (rev 5280) @@ -1447,10 +1447,7 @@ static void gen_iwmmxt_movl_wRn_T0_T1(int rn) { - tcg_gen_extu_i32_i64(cpu_V0, cpu_T[0]); - tcg_gen_extu_i32_i64(cpu_V1, cpu_T[0]); - tcg_gen_shli_i64(cpu_V1, cpu_V1, 32); - tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1); + tcg_gen_concat_i32_i64(cpu_V0, cpu_T[0], cpu_T[1]); iwmmxt_store_reg(cpu_V0, rn); } @@ -4663,14 +4660,11 @@ } else { tmp = neon_load_reg(rm + pass, 0); gen_neon_shift_narrow(size, tmp, tmp2, q, u); - tcg_gen_extu_i32_i64(cpu_V0, tmp); + tmp3 = neon_load_reg(rm + pass, 1); + gen_neon_shift_narrow(size, tmp3, tmp2, q, u); + tcg_gen_concat_i32_i64(cpu_V0, tmp, tmp3); dead_tmp(tmp); - tmp = neon_load_reg(rm + pass, 1); - gen_neon_shift_narrow(size, tmp, tmp2, q, u); - tcg_gen_extu_i32_i64(cpu_V1, tmp); - dead_tmp(tmp); - tcg_gen_shli_i64(cpu_V1, cpu_V1, 32); - tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1); + dead_tmp(tmp3); } tmp = new_tmp(); if (op == 8 && !u) { @@ -5600,7 +5594,7 @@ TCGv tmp; TCGv tmp2; - /* Load 64-bit value rd:rn. */ + /* Load value and extend to 64 bits. */ tmp = tcg_temp_new(TCG_TYPE_I64); tmp2 = load_reg(s, rlow); tcg_gen_extu_i32_i64(tmp, tmp2); @@ -5612,20 +5606,17 @@ static void gen_addq(DisasContext *s, TCGv val, int rlow, int rhigh) { TCGv tmp; - TCGv tmp2; + TCGv tmpl; + TCGv tmph; /* Load 64-bit value rd:rn. */ + tmpl = load_reg(s, rlow); + tmph = load_reg(s, rhigh); tmp = tcg_temp_new(TCG_TYPE_I64); - tmp2 = load_reg(s, rhigh); - tcg_gen_extu_i32_i64(tmp, tmp2); - dead_tmp(tmp2); - tcg_gen_shli_i64(tmp, tmp, 32); + tcg_gen_concat_i32_i64(tmp, tmpl, tmph); + dead_tmp(tmpl); + dead_tmp(tmph); tcg_gen_add_i64(val, val, tmp); - - tmp2 = load_reg(s, rlow); - tcg_gen_extu_i32_i64(tmp, tmp2); - dead_tmp(tmp2); - tcg_gen_add_i64(val, val, tmp); } /* Set N and Z flags from a 64-bit value. */ Modified: trunk/target-mips/translate.c =================================================================== --- trunk/target-mips/translate.c 2008-09-21 02:39:45 UTC (rev 5279) +++ trunk/target-mips/translate.c 2008-09-21 13:48:32 UTC (rev 5280) @@ -693,13 +693,7 @@ if (ctx->hflags & MIPS_HFLAG_F64) tcg_gen_mov_i64(t, fpu_fpr64[reg]); else { - TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64); - - tcg_gen_extu_i32_i64(t, fpu_fpr32[reg | 1]); - tcg_gen_shli_i64(t, t, 32); - tcg_gen_extu_i32_i64(r_tmp2, fpu_fpr32[reg & ~1]); - tcg_gen_or_i64(t, t, r_tmp2); - tcg_temp_free(r_tmp2); + tcg_gen_concat_i32_i64(t, fpu_fpr32[reg & ~1], fpu_fpr32[reg | 1]); } } @@ -6546,22 +6540,17 @@ case FOP(38, 16): check_cp1_64bitmode(ctx); { - TCGv fp64_0 = tcg_temp_new(TCG_TYPE_I64); - TCGv fp64_1 = tcg_temp_new(TCG_TYPE_I64); + TCGv fp64 = tcg_temp_new(TCG_TYPE_I64); TCGv fp32_0 = tcg_temp_new(TCG_TYPE_I32); TCGv fp32_1 = tcg_temp_new(TCG_TYPE_I32); gen_load_fpr32(fp32_0, fs); gen_load_fpr32(fp32_1, ft); - tcg_gen_extu_i32_i64(fp64_0, fp32_0); - tcg_gen_extu_i32_i64(fp64_1, fp32_1); - tcg_temp_free(fp32_0); + tcg_gen_concat_i32_i64(fp64, fp32_0, fp32_1); tcg_temp_free(fp32_1); - tcg_gen_shli_i64(fp64_1, fp64_1, 32); - tcg_gen_or_i64(fp64_0, fp64_0, fp64_1); - tcg_temp_free(fp64_1); - gen_store_fpr64(ctx, fp64_0, fd); - tcg_temp_free(fp64_0); + tcg_temp_free(fp32_0); + gen_store_fpr64(ctx, fp64, fd); + tcg_temp_free(fp64); } opn = "cvt.ps.s"; break; Modified: trunk/target-ppc/translate.c =================================================================== --- trunk/target-ppc/translate.c 2008-09-21 02:39:45 UTC (rev 5279) +++ trunk/target-ppc/translate.c 2008-09-21 13:48:32 UTC (rev 5280) @@ -5300,12 +5300,7 @@ #if defined(TARGET_PPC64) tcg_gen_mov_i64(t, cpu_gpr[reg]); #else - tcg_gen_extu_i32_i64(t, cpu_gprh[reg]); - tcg_gen_shli_i64(t, t, 32); - TCGv tmp = tcg_temp_local_new(TCG_TYPE_I64); - tcg_gen_extu_i32_i64(tmp, cpu_gpr[reg]); - tcg_gen_or_i64(t, t, tmp); - tcg_temp_free(tmp); + tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]); #endif } Modified: trunk/target-sh4/translate.c =================================================================== --- trunk/target-sh4/translate.c 2008-09-21 02:39:45 UTC (rev 5279) +++ trunk/target-sh4/translate.c 2008-09-21 13:48:32 UTC (rev 5280) @@ -400,15 +400,12 @@ static inline void gen_load_fpr64(TCGv t, int reg) { TCGv tmp1 = tcg_temp_new(TCG_TYPE_I32); - TCGv tmp2 = tcg_temp_new(TCG_TYPE_I64); + TCGv tmp2 = tcg_temp_new(TCG_TYPE_I32); tcg_gen_ld_i32(tmp1, cpu_env, offsetof(CPUState, fregs[reg])); - tcg_gen_extu_i32_i64(t, tmp1); - tcg_gen_shli_i64(t, t, 32); - tcg_gen_ld_i32(tmp1, cpu_env, offsetof(CPUState, fregs[reg + 1])); - tcg_gen_extu_i32_i64(tmp2, tmp1); + tcg_gen_ld_i32(tmp2, cpu_env, offsetof(CPUState, fregs[reg + 1])); + tcg_gen_concat_i32_i64(t, tmp2, tmp1); tcg_temp_free(tmp1); - tcg_gen_or_i64(t, t, tmp2); tcg_temp_free(tmp2); } Modified: trunk/tcg/README =================================================================== --- trunk/tcg/README 2008-09-21 02:39:45 UTC (rev 5279) +++ trunk/tcg/README 2008-09-21 13:48:32 UTC (rev 5280) @@ -265,6 +265,10 @@ * trunc_i64_i32 t0, t1 Truncate t1 (64 bit) to t0 (32 bit) +* concat_i32_i64 t0, t1, t2 +Construct t0 (64-bit) taking the low half from t1 (32 bit) and the high half +from t2 (32 bit). + ********* Load/Store * ld_i32/i64 t0, t1, offset Modified: trunk/tcg/tcg-op.h =================================================================== --- trunk/tcg/tcg-op.h 2008-09-21 02:39:45 UTC (rev 5279) +++ trunk/tcg/tcg-op.h 2008-09-21 13:48:32 UTC (rev 5280) @@ -1395,6 +1395,23 @@ } #endif +static inline void tcg_gen_concat_i32_i64(TCGv dest, TCGv low, TCGv high) +{ +#if TCG_TARGET_REG_BITS == 32 + tcg_gen_mov_i32(dest, low); + tcg_gen_mov_i32(TCGV_HIGH(dest), high); +#else + TCGv tmp = tcg_temp_new (TCG_TYPE_I64); + /* This extension is only needed for type correctness. + We may be able to do better given target specific information. */ + tcg_gen_extu_i32_i64(tmp, high); + tcg_gen_shli_i64(tmp, tmp, 32); + tcg_gen_extu_i32_i64(dest, low); + tcg_gen_or_i64(dest, dest, tmp); + tcg_temp_free(tmp); +#endif +} + /***************************************/ /* QEMU specific operations. Their type depend on the QEMU CPU type. */