From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KivJO-0000Ke-Bx for qemu-devel@nongnu.org; Thu, 25 Sep 2008 14:11:34 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KivJN-0000K5-Og for qemu-devel@nongnu.org; Thu, 25 Sep 2008 14:11:34 -0400 Received: from [199.232.76.173] (port=47536 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KivJN-0000Ju-Ej for qemu-devel@nongnu.org; Thu, 25 Sep 2008 14:11:33 -0400 Received: from savannah.gnu.org ([199.232.41.3]:51006 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1KivJN-000064-Ez for qemu-devel@nongnu.org; Thu, 25 Sep 2008 14:11:33 -0400 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.63) (envelope-from ) id 1KivJL-000547-DK for qemu-devel@nongnu.org; Thu, 25 Sep 2008 18:11:31 +0000 Received: from balrog by cvs.savannah.gnu.org with local (Exim 4.63) (envelope-from ) id 1KivJL-000543-32 for qemu-devel@nongnu.org; Thu, 25 Sep 2008 18:11:31 +0000 MIME-Version: 1.0 Errors-To: balrog Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Andrzej Zaborowski Message-Id: Date: Thu, 25 Sep 2008 18:11:31 +0000 Subject: [Qemu-devel] [5317] Core 2 Duo specification (Alexander Graf). Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 5317 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=5317 Author: balrog Date: 2008-09-25 18:11:30 +0000 (Thu, 25 Sep 2008) Log Message: ----------- Core 2 Duo specification (Alexander Graf). This patch adds a Core 2 Duo CPU to the available CPU types. The CPU definition tries to resemble a real CPU as good as possible, whilst not exposing features qemu does not implement. The patch also includes some minor additions that Core 2 Duo CPUs have: - New MSR: MSR_IA32_PERF_STATUS - CPUID up to level 5 (cache info and mwait) Signed-off-by: Alexander Graf Modified Paths: -------------- trunk/target-i386/cpu.h trunk/target-i386/helper.c trunk/target-i386/op_helper.c Modified: trunk/target-i386/cpu.h =================================================================== --- trunk/target-i386/cpu.h 2008-09-25 18:08:05 UTC (rev 5316) +++ trunk/target-i386/cpu.h 2008-09-25 18:11:30 UTC (rev 5317) @@ -242,6 +242,8 @@ #define MSR_MCG_STATUS 0x17a #define MSR_MCG_CTL 0x17b +#define MSR_IA32_PERF_STATUS 0x198 + #define MSR_PAT 0x277 #define MSR_EFER 0xc0000080 @@ -341,6 +343,9 @@ #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ +#define CPUID_MWAIT_IBE (1 << 1) /* Interrupts can exit capability */ +#define CPUID_MWAIT_EMX (0 << 1) /* enumeration supported */ + #define EXCP00_DIVZ 0 #define EXCP01_SSTP 1 #define EXCP02_NMI 2 Modified: trunk/target-i386/helper.c =================================================================== --- trunk/target-i386/helper.c 2008-09-25 18:08:05 UTC (rev 5316) +++ trunk/target-i386/helper.c 2008-09-25 18:11:30 UTC (rev 5317) @@ -165,6 +165,24 @@ .xlevel = 0x8000000A, .model_id = "QEMU Virtual CPU version " QEMU_VERSION, }, + { + .name = "core2duo", + /* original is on level 10 */ + .level = 5, + .family = 6, + .model = 15, + .stepping = 11, + /* the original CPU does have many more features that are + * not implemented yet */ + .features = PPRO_FEATURES | + CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | + CPUID_PSE36, + .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, + .ext2_features = (PPRO_FEATURES & 0x0183F3FF) | + CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, + .xlevel = 0x8000000A, + .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", + }, #endif { .name = "qemu32", Modified: trunk/target-i386/op_helper.c =================================================================== --- trunk/target-i386/op_helper.c 2008-09-25 18:08:05 UTC (rev 5316) +++ trunk/target-i386/op_helper.c 2008-09-25 18:11:30 UTC (rev 5317) @@ -1919,6 +1919,43 @@ ECX = 0; EDX = 0x2c307d; break; + case 4: + /* cache info: needed for Core compatibility */ + switch (ECX) { + case 0: /* L1 dcache info */ + EAX = 0x0000121; + EBX = 0x1c0003f; + ECX = 0x000003f; + EDX = 0x0000001; + break; + case 1: /* L1 icache info */ + EAX = 0x0000122; + EBX = 0x1c0003f; + ECX = 0x000003f; + EDX = 0x0000001; + break; + case 2: /* L2 cache info */ + EAX = 0x0000143; + EBX = 0x3c0003f; + ECX = 0x0000fff; + EDX = 0x0000001; + break; + default: /* end of info */ + EAX = 0; + EBX = 0; + ECX = 0; + EDX = 0; + break; + } + + break; + case 5: + /* mwait info: needed for Core compatibility */ + EAX = 0; /* Smallest monitor-line size in bytes */ + EBX = 0; /* Largest monitor-line size in bytes */ + ECX = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; + EDX = 0; + break; case 0x80000000: EAX = env->cpuid_xlevel; EBX = env->cpuid_vendor1; @@ -3089,6 +3126,12 @@ case MSR_VM_HSAVE_PA: env->vm_hsave = val; break; + case MSR_IA32_PERF_STATUS: + /* tsc_increment_by_tick */ + val = 1000ULL; + /* CPU multiplier */ + val |= (((uint64_t)4ULL) << 40); + break; #ifdef TARGET_X86_64 case MSR_LSTAR: env->lstar = val;