From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KsFQ7-0001I1-4P for qemu-devel@nongnu.org; Tue, 21 Oct 2008 07:29:03 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KsFQ6-0001Hc-AS for qemu-devel@nongnu.org; Tue, 21 Oct 2008 07:29:02 -0400 Received: from [199.232.76.173] (port=59335 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KsFQ6-0001HW-5z for qemu-devel@nongnu.org; Tue, 21 Oct 2008 07:29:02 -0400 Received: from savannah.gnu.org ([199.232.41.3]:41558 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1KsFQ5-0000FP-P0 for qemu-devel@nongnu.org; Tue, 21 Oct 2008 07:29:02 -0400 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.63) (envelope-from ) id 1KsFQ4-0003r6-8U for qemu-devel@nongnu.org; Tue, 21 Oct 2008 11:29:00 +0000 Received: from aurel32 by cvs.savannah.gnu.org with local (Exim 4.63) (envelope-from ) id 1KsFQ4-0003r2-3I for qemu-devel@nongnu.org; Tue, 21 Oct 2008 11:29:00 +0000 MIME-Version: 1.0 Errors-To: aurel32 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Aurelien Jarno Message-Id: Date: Tue, 21 Oct 2008 11:29:00 +0000 Subject: [Qemu-devel] [5501] TCG: add logical operations found on alpha and powerpc processors Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 5501 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=5501 Author: aurel32 Date: 2008-10-21 11:28:59 +0000 (Tue, 21 Oct 2008) Log Message: ----------- TCG: add logical operations found on alpha and powerpc processors - andc_i32/i64 t0, t1, t2 - eqv_i32/i64 t0, t1, t2 - nand_i32/i64 t0, t1, t2 - nor_i32/i64 t0, t1, t2 - orc_i32/i64 t0, t1, t2 Signed-off-by: Aurelien Jarno Modified Paths: -------------- trunk/tcg/README trunk/tcg/tcg-op.h Modified: trunk/tcg/README =================================================================== --- trunk/tcg/README 2008-10-21 11:28:46 UTC (rev 5500) +++ trunk/tcg/README 2008-10-21 11:28:59 UTC (rev 5501) @@ -205,6 +205,26 @@ t0=~t1 +* andc_i32/i64 t0, t1, t2 + +t0=t1&~t2 + +* eqv_i32/i64 t0, t1, t2 + +t0=~(t1^t2) + +* nand_i32/i64 t0, t1, t2 + +t0=~(t1&t2) + +* nor_i32/i64 t0, t1, t2 + +t0=~(t1|t2) + +* orc_i32/i64 t0, t1, t2 + +t0=t1|~t2 + ********* Shifts * shl_i32/i64 t0, t1, t2 Modified: trunk/tcg/tcg-op.h =================================================================== --- trunk/tcg/tcg-op.h 2008-10-21 11:28:46 UTC (rev 5500) +++ trunk/tcg/tcg-op.h 2008-10-21 11:28:59 UTC (rev 5501) @@ -1425,6 +1425,96 @@ #endif } +static inline void tcg_gen_andc_i32(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv t0; + t0 = tcg_temp_new(TCG_TYPE_I32); + tcg_gen_not_i32(t0, arg2); + tcg_gen_and_i32(ret, arg1, t0); + tcg_temp_free(t0); +} + +static inline void tcg_gen_andc_i64(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv t0; + t0 = tcg_temp_new(TCG_TYPE_I64); + tcg_gen_not_i64(t0, arg2); + tcg_gen_and_i64(ret, arg1, t0); + tcg_temp_free(t0); +} + +static inline void tcg_gen_eqv_i32(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv t0; + t0 = tcg_temp_new(TCG_TYPE_I32); + tcg_gen_xor_i32(t0, arg1, arg2); + tcg_gen_not_i32(ret, t0); + tcg_temp_free(t0); +} + +static inline void tcg_gen_eqv_i64(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv t0; + t0 = tcg_temp_new(TCG_TYPE_I64); + tcg_gen_xor_i64(t0, arg1, arg2); + tcg_gen_not_i64(ret, t0); + tcg_temp_free(t0); +} + +static inline void tcg_gen_nand_i32(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv t0; + t0 = tcg_temp_new(TCG_TYPE_I32); + tcg_gen_and_i32(t0, arg1, arg2); + tcg_gen_not_i32(ret, t0); + tcg_temp_free(t0); +} + +static inline void tcg_gen_nand_i64(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv t0; + t0 = tcg_temp_new(TCG_TYPE_I64); + tcg_gen_and_i64(t0, arg1, arg2); + tcg_gen_not_i64(ret, t0); + tcg_temp_free(t0); +} + +static inline void tcg_gen_nor_i32(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv t0; + t0 = tcg_temp_new(TCG_TYPE_I32); + tcg_gen_or_i32(t0, arg1, arg2); + tcg_gen_not_i32(ret, t0); + tcg_temp_free(t0); +} + +static inline void tcg_gen_nor_i64(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv t0; + t0 = tcg_temp_new(TCG_TYPE_I64); + tcg_gen_or_i64(t0, arg1, arg2); + tcg_gen_not_i64(ret, t0); + tcg_temp_free(t0); +} + +static inline void tcg_gen_orc_i32(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv t0; + t0 = tcg_temp_new(TCG_TYPE_I32); + tcg_gen_not_i32(t0, arg2); + tcg_gen_or_i32(ret, arg1, t0); + tcg_temp_free(t0); +} + +static inline void tcg_gen_orc_i64(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv t0; + t0 = tcg_temp_new(TCG_TYPE_I64); + tcg_gen_not_i64(t0, arg2); + tcg_gen_or_i64(ret, arg1, t0); + tcg_temp_free(t0); +} + /***************************************/ /* QEMU specific operations. Their type depend on the QEMU CPU type. */ @@ -1678,6 +1768,11 @@ #define tcg_gen_ext32u_tl tcg_gen_ext32u_i64 #define tcg_gen_ext32s_tl tcg_gen_ext32s_i64 #define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64 +#define tcg_gen_andc_tl tcg_gen_andc_i64 +#define tcg_gen_eqv_tl tcg_gen_eqv_i64 +#define tcg_gen_nand_tl tcg_gen_nand_i64 +#define tcg_gen_nor_tl tcg_gen_nor_i64 +#define tcg_gen_orc_tl tcg_gen_orc_i64 #define tcg_const_tl tcg_const_i64 #else #define TCG_TYPE_TL TCG_TYPE_I32 @@ -1730,6 +1825,11 @@ #define tcg_gen_ext32u_tl tcg_gen_mov_i32 #define tcg_gen_ext32s_tl tcg_gen_mov_i32 #define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64 +#define tcg_gen_andc_tl tcg_gen_andc_i32 +#define tcg_gen_eqv_tl tcg_gen_eqv_i32 +#define tcg_gen_nand_tl tcg_gen_nand_i32 +#define tcg_gen_nor_tl tcg_gen_nor_i32 +#define tcg_gen_orc_tl tcg_gen_orc_i32 #define tcg_const_tl tcg_const_i32 #endif