From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Kusn2-0004zW-9l for qemu-devel@nongnu.org; Tue, 28 Oct 2008 13:55:36 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Kusn1-0004zK-Mg for qemu-devel@nongnu.org; Tue, 28 Oct 2008 13:55:35 -0400 Received: from [199.232.76.173] (port=42841 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Kusn1-0004zH-KH for qemu-devel@nongnu.org; Tue, 28 Oct 2008 13:55:35 -0400 Received: from savannah.gnu.org ([199.232.41.3]:46626 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1Kusn1-0000LB-Fr for qemu-devel@nongnu.org; Tue, 28 Oct 2008 13:55:35 -0400 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.63) (envelope-from ) id 1Kusn0-0005vz-4W for qemu-devel@nongnu.org; Tue, 28 Oct 2008 17:55:34 +0000 Received: from blueswir1 by cvs.savannah.gnu.org with local (Exim 4.63) (envelope-from ) id 1Kusmz-0005vv-FL for qemu-devel@nongnu.org; Tue, 28 Oct 2008 17:55:33 +0000 MIME-Version: 1.0 Errors-To: blueswir1 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Blue Swirl Message-Id: Date: Tue, 28 Oct 2008 17:55:33 +0000 Subject: [Qemu-devel] [5568] Sun4c cleanups (Robert Reif) Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 5568 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=5568 Author: blueswir1 Date: 2008-10-28 17:55:32 +0000 (Tue, 28 Oct 2008) Log Message: ----------- Sun4c cleanups (Robert Reif) Modified Paths: -------------- trunk/hw/sun4m.c Modified: trunk/hw/sun4m.c =================================================================== --- trunk/hw/sun4m.c 2008-10-28 14:08:49 UTC (rev 5567) +++ trunk/hw/sun4m.c 2008-10-28 17:55:32 UTC (rev 5568) @@ -99,7 +99,7 @@ long vram_size, nvram_size; // IRQ numbers are not PIL ones, but master interrupt controller // register bit numbers - int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq; + int esp_irq, le_irq, clock_irq, clock1_irq; int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq; uint8_t nvram_machine_id; uint16_t machine_id; @@ -135,12 +135,12 @@ target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; target_phys_addr_t serial_base, fd_base; target_phys_addr_t idreg_base, dma_base, esp_base, le_base; - target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base; + target_phys_addr_t tcx_base, aux1_base; long vram_size, nvram_size; // IRQ numbers are not PIL ones, but master interrupt controller // register bit numbers - int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq; - int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq; + int esp_irq, le_irq, clock_irq, clock1_irq; + int ser_irq, ms_kb_irq, fd_irq, me_irq; uint8_t nvram_machine_id; uint16_t machine_id; uint32_t iommu_version; @@ -1440,7 +1440,6 @@ { .iommu_base = 0xf8000000, .tcx_base = 0xfe000000, - .cs_base = -1, .slavio_base = 0xf6000000, .intctl_base = 0xf5000000, .counter_base = 0xf3000000, @@ -1451,9 +1450,7 @@ .dma_base = 0xf8400000, .esp_base = 0xf8800000, .le_base = 0xf8c00000, - .apc_base = -1, .aux1_base = 0xf7400003, - .aux2_base = -1, .vram_size = 0x00100000, .nvram_size = 0x800, .esp_irq = 2, @@ -1464,7 +1461,6 @@ .ser_irq = 1, .fd_irq = 1, .me_irq = 1, - .cs_irq = -1, .nvram_machine_id = 0x55, .machine_id = ss2_id, .max_mem = 0x10000000, @@ -1579,8 +1575,7 @@ slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], serial_hds[1], serial_hds[0]); - slavio_misc = slavio_misc_init(0, hwdef->apc_base, - hwdef->aux1_base, hwdef->aux2_base, + slavio_misc = slavio_misc_init(0, -1, hwdef->aux1_base, -1, slavio_irq[hwdef->me_irq], env, &fdc_tc); if (hwdef->fd_base != (target_phys_addr_t)-1) {