From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KzE4I-0006xK-80 for qemu-devel@nongnu.org; Sun, 09 Nov 2008 12:27:22 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KzE4H-0006wn-ND for qemu-devel@nongnu.org; Sun, 09 Nov 2008 12:27:21 -0500 Received: from [199.232.76.173] (port=47931 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KzE4H-0006wX-7C for qemu-devel@nongnu.org; Sun, 09 Nov 2008 12:27:21 -0500 Received: from savannah.gnu.org ([199.232.41.3]:42870 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1KzE4G-0008L1-Nz for qemu-devel@nongnu.org; Sun, 09 Nov 2008 12:27:20 -0500 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.63) (envelope-from ) id 1KzE4G-0001dc-Ae for qemu-devel@nongnu.org; Sun, 09 Nov 2008 17:27:20 +0000 Received: from aurel32 by cvs.savannah.gnu.org with local (Exim 4.63) (envelope-from ) id 1KzE4G-0001dX-2S for qemu-devel@nongnu.org; Sun, 09 Nov 2008 17:27:20 +0000 MIME-Version: 1.0 Errors-To: aurel32 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Aurelien Jarno Message-Id: Date: Sun, 09 Nov 2008 17:27:20 +0000 Subject: [Qemu-devel] [5658] target-ppc: gen_op_arith_divw() & gen_op_arith_divd fixes Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 5658 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=5658 Author: aurel32 Date: 2008-11-09 17:27:19 +0000 (Sun, 09 Nov 2008) Log Message: ----------- target-ppc: gen_op_arith_divw() & gen_op_arith_divd fixes gen_op_arith_divw(): - "deoptimize" gen_op_arith_divw to make it more readable. - Correctly free TCG temp variable gen_op_arith_divd(): - Call the right function. Signed-off-by: Aurelien Jarno Modified Paths: -------------- trunk/target-ppc/translate.c Modified: trunk/target-ppc/translate.c =================================================================== --- trunk/target-ppc/translate.c 2008-11-09 17:27:11 UTC (rev 5657) +++ trunk/target-ppc/translate.c 2008-11-09 17:27:19 UTC (rev 5658) @@ -1067,33 +1067,22 @@ static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2, int sign, int compute_ov) { - int l1, l2, l3; - TCGv t0, t1, t2; + int l1 = gen_new_label(); + int l2 = gen_new_label(); + TCGv t0 = tcg_temp_local_new(TCG_TYPE_I32); + TCGv t1 = tcg_temp_local_new(TCG_TYPE_I32); -#if defined(TARGET_PPC64) - t0 = tcg_temp_local_new(TCG_TYPE_I32); - t1 = t0; - t2 = tcg_temp_local_new(TCG_TYPE_I32); - tcg_gen_trunc_i64_i32(t1, arg1); - tcg_gen_trunc_i64_i32(t2, arg2); -#else - t0 = ret; - t1 = arg1; - t2 = arg2; -#endif - l1 = gen_new_label(); - l2 = gen_new_label(); - tcg_gen_brcondi_i32(TCG_COND_EQ, t2, 0, l1); + tcg_gen_trunc_tl_i32(t0, arg1); + tcg_gen_trunc_tl_i32(t1, arg2); + tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1); if (sign) { - l3 = gen_new_label(); - tcg_gen_brcondi_i32(TCG_COND_NE, t2, -1, l3); - tcg_gen_brcondi_i32(TCG_COND_EQ, t1, INT32_MIN, l1); + int l3 = gen_new_label(); + tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3); + tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1); gen_set_label(l3); - } - if (sign) { - tcg_gen_div_i32(t0, t1, t2); + tcg_gen_div_i32(t0, t0, t1); } else { - tcg_gen_divu_i32(t0, t1, t2); + tcg_gen_divu_i32(t0, t0, t1); } if (compute_ov) { tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); @@ -1101,7 +1090,7 @@ tcg_gen_br(l2); gen_set_label(l1); if (sign) { - tcg_gen_sari_i32(t0, t1, 31); + tcg_gen_sari_i32(t0, t0, 31); } else { tcg_gen_movi_i32(t0, 0); } @@ -1109,10 +1098,9 @@ tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); } gen_set_label(l2); -#if defined(TARGET_PPC64) - tcg_gen_extu_i32_i64(ret, t0); + tcg_gen_extu_i32_tl(ret, t0); tcg_temp_free(t0); -#endif + tcg_temp_free(t1); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx, ret); } @@ -1131,22 +1119,18 @@ GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); #if defined(TARGET_PPC64) -static always_inline void gen_op_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2, - int sign, int compute_ov) +static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2, + int sign, int compute_ov) { - int l1, l2, l3; + int l1 = gen_new_label(); + int l2 = gen_new_label(); - l1 = gen_new_label(); - l2 = gen_new_label(); - tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1); if (sign) { - l3 = gen_new_label(); + int l3 = gen_new_label(); tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3); tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1); gen_set_label(l3); - } - if (sign) { tcg_gen_div_i64(ret, arg1, arg2); } else { tcg_gen_divu_i64(ret, arg1, arg2); @@ -1171,9 +1155,9 @@ #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \ { \ - gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ - cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ - sign, compute_ov); \ + gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ + cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ + sign, compute_ov); \ } /* divwu divwu. divwuo divwuo. */ GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);