[Qemu-devel] [5659] target-ppc: fixes for gen_op_neg()

[Qemu-devel] [5659] target-ppc: fixes for gen_op_neg()

[Aurelien Jarno]

Revision: 5659
          http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=5659
Author:   aurel32
Date:     2008-11-09 17:27:27 +0000 (Sun, 09 Nov 2008)

Log Message:
-----------
target-ppc: fixes for gen_op_neg()

- Rename to gen_op_arith_neg for consistency with other functions.
- Correctly free TCG temp variable.
- Fix the return value in 64-bit mode in case of overflow.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

Modified Paths:
--------------
    trunk/target-ppc/translate.c

Modified: trunk/target-ppc/translate.c
===================================================================
--- trunk/target-ppc/translate.c	2008-11-09 17:27:19 UTC (rev 5658)
+++ trunk/target-ppc/translate.c	2008-11-09 17:27:27 UTC (rev 5659)
@@ -1288,44 +1288,43 @@
 #endif
 
 /* neg neg. nego nego. */
-static always_inline void gen_op_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
+static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
 {
-    int l1, l2;
-
-    l1 = gen_new_label();
-    l2 = gen_new_label();
+    int l1 = gen_new_label();
+    int l2 = gen_new_label();
+    TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
 #if defined(TARGET_PPC64)
     if (ctx->sf_mode) {
-        tcg_gen_brcondi_tl(TCG_COND_EQ, arg1, INT64_MIN, l1);
-    } else {
-        TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
-	tcg_gen_ext32s_tl(t0, arg1);
+        tcg_gen_movi_tl(t0, arg1);
+        tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
+    } else
+#endif
+    {
+        tcg_gen_ext32s_tl(t0, arg1);
         tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
     }
-#else
-        tcg_gen_brcondi_tl(TCG_COND_EQ, arg1, INT32_MIN, l1);
-#endif
     tcg_gen_neg_tl(ret, arg1);
     if (ov_check) {
         tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
     }
     tcg_gen_br(l2);
     gen_set_label(l1);
-    tcg_gen_mov_tl(ret, arg1);
+    tcg_gen_mov_tl(ret, t0);
     if (ov_check) {
         tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
     }
     gen_set_label(l2);
+    tcg_temp_free(t0);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx, ret);
 }
 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER)
 {
-    gen_op_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
+    gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
 }
 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER)
 {
-    gen_op_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
+    gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
 }
 
 /* Common subf function */