From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Kzraq-0001bQ-1o for qemu-devel@nongnu.org; Tue, 11 Nov 2008 06:39:36 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Kzrap-0001ac-8O for qemu-devel@nongnu.org; Tue, 11 Nov 2008 06:39:35 -0500 Received: from [199.232.76.173] (port=55198 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Kzrap-0001aU-4F for qemu-devel@nongnu.org; Tue, 11 Nov 2008 06:39:35 -0500 Received: from savannah.gnu.org ([199.232.41.3]:58536 helo=sv.gnu.org) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1Kzrao-0005kD-Ss for qemu-devel@nongnu.org; Tue, 11 Nov 2008 06:39:35 -0500 Received: from cvs.savannah.gnu.org ([199.232.41.69]) by sv.gnu.org with esmtp (Exim 4.63) (envelope-from ) id 1Kzrao-0003V5-3m for qemu-devel@nongnu.org; Tue, 11 Nov 2008 11:39:34 +0000 Received: from aurel32 by cvs.savannah.gnu.org with local (Exim 4.63) (envelope-from ) id 1Kzran-0003Uz-KW for qemu-devel@nongnu.org; Tue, 11 Nov 2008 11:39:33 +0000 MIME-Version: 1.0 Errors-To: aurel32 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Aurelien Jarno Message-Id: Date: Tue, 11 Nov 2008 11:39:33 +0000 Subject: [Qemu-devel] [5677] target-mips: optimize gen_op_addr_add() (2/2) Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Revision: 5677 http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=5677 Author: aurel32 Date: 2008-11-11 11:39:33 +0000 (Tue, 11 Nov 2008) Log Message: ----------- target-mips: optimize gen_op_addr_add() (2/2) Instead of dynamically generating different code depending on the UX flag, add a new flag in ctx->flags to generate different code. Signed-off-by: Aurelien Jarno Modified Paths: -------------- trunk/target-mips/cpu.h trunk/target-mips/exec.h trunk/target-mips/translate.c Modified: trunk/target-mips/cpu.h =================================================================== --- trunk/target-mips/cpu.h 2008-11-11 11:36:52 UTC (rev 5676) +++ trunk/target-mips/cpu.h 2008-11-11 11:39:33 UTC (rev 5677) @@ -411,7 +411,7 @@ int error_code; uint32_t hflags; /* CPU State */ /* TMASK defines different execution modes */ -#define MIPS_HFLAG_TMASK 0x01FF +#define MIPS_HFLAG_TMASK 0x03FF #define MIPS_HFLAG_MODE 0x0007 /* execution modes */ /* The KSU flags must be the lowest bits in hflags. The flag order must be the same as defined for CP0 Status. This allows to use @@ -430,15 +430,16 @@ and RSQRT.D. */ #define MIPS_HFLAG_COP1X 0x0080 /* COP1X instructions enabled */ #define MIPS_HFLAG_RE 0x0100 /* Reversed endianness */ +#define MIPS_HFLAG_UX 0x0200 /* 64-bit user mode */ /* If translation is interrupted between the branch instruction and * the delay slot, record what type of branch it is so that we can * resume translation properly. It might be possible to reduce * this from three bits to two. */ -#define MIPS_HFLAG_BMASK 0x0e00 -#define MIPS_HFLAG_B 0x0200 /* Unconditional branch */ -#define MIPS_HFLAG_BC 0x0400 /* Conditional branch */ -#define MIPS_HFLAG_BL 0x0600 /* Likely branch */ -#define MIPS_HFLAG_BR 0x0800 /* branch to register (can't link TB) */ +#define MIPS_HFLAG_BMASK 0x1C00 +#define MIPS_HFLAG_B 0x0400 /* Unconditional branch */ +#define MIPS_HFLAG_BC 0x0800 /* Conditional branch */ +#define MIPS_HFLAG_BL 0x0C00 /* Likely branch */ +#define MIPS_HFLAG_BR 0x1000 /* branch to register (can't link TB) */ target_ulong btarget; /* Jump / branch target */ int bcond; /* Branch condition (if needed) */ Modified: trunk/target-mips/exec.h =================================================================== --- trunk/target-mips/exec.h 2008-11-11 11:36:52 UTC (rev 5676) +++ trunk/target-mips/exec.h 2008-11-11 11:39:33 UTC (rev 5677) @@ -66,7 +66,8 @@ static inline void compute_hflags(CPUState *env) { env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | - MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU); + MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU | + MIPS_HFLAG_UX); if (!(env->CP0_Status & (1 << CP0St_EXL)) && !(env->CP0_Status & (1 << CP0St_ERL)) && !(env->hflags & MIPS_HFLAG_DM)) { @@ -77,6 +78,8 @@ (env->CP0_Status & (1 << CP0St_PX)) || (env->CP0_Status & (1 << CP0St_UX))) env->hflags |= MIPS_HFLAG_64; + if (env->CP0_Status & (1 << CP0St_UX)) + env->hflags |= MIPS_HFLAG_UX; #endif if ((env->CP0_Status & (1 << CP0St_CU0)) || !(env->hflags & MIPS_HFLAG_KSU)) Modified: trunk/target-mips/translate.c =================================================================== --- trunk/target-mips/translate.c 2008-11-11 11:36:52 UTC (rev 5676) +++ trunk/target-mips/translate.c 2008-11-11 11:39:33 UTC (rev 5677) @@ -902,16 +902,9 @@ /* For compatibility with 32-bit code, data reference in user mode with Status_UX = 0 should be casted to 32-bit and sign extended. See the MIPS64 PRA manual, section 4.10. */ - if ((ctx->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) { - int l1 = gen_new_label(); - TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32); - - tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Status)); - tcg_gen_andi_i32(r_tmp, r_tmp, (1 << CP0St_UX)); - tcg_gen_brcondi_i32(TCG_COND_NE, r_tmp, 0, l1); + if (((ctx->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) && + !(ctx->hflags & MIPS_HFLAG_UX)) { tcg_gen_ext32s_i64(t0, t0); - gen_set_label(l1); - tcg_temp_free(r_tmp); } #endif }